公开(公告)号：US10150668B2

公开(公告)日：2018-12-11

申请号：US15484765

申请日：2017-04-11

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: H01L27/14 ,  B81C1/00 ,  B81B7/00

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US20170217766A1

公开(公告)日：2017-08-03

申请号：US15484765

申请日：2017-04-11

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US09550670B2

公开(公告)日：2017-01-24

申请号：US14731211

申请日：2015-06-04

Applicant: Intel IP Corporation

Inventor： Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner ,  Reinhard Mahnkopf ,  Andreas Augustin ,  Christian Mueller

IPC: H01L21/00 ,  B81C1/00 ,  B81B7/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: B81C1/00666 ,  B81B7/0054 ,  B81C1/00261 ,  B81C1/00349 ,  B81C2203/0136 ,  B81C2203/0154 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73277 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.

Abstract translation: 描述了用于集成微机电系统（MEMS）的应力缓冲层。 例如，半导体封装包括具有第一和第二表面的衬底，第二表面具有外部导电触点阵列。 微机电系统（MEMS）部件设置在基板的第一表面上方。 缓冲层设置在MEMS部件上方，缓冲层具有第一杨氏模量。 模具化合物设置在缓冲层上方，模塑料具有高于第一杨氏模量的第二杨氏模量。

公开(公告)号：US20160260689A1

公开(公告)日：2016-09-08

申请号：US14649104

申请日：2014-07-07

Applicant: INTEL IP CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner

IPC: H01L25/065 ,  H01L21/54 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/54 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3178 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/97 ,  H01L25/065 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/15331 ,  H05K1/11 ,  H05K2201/10515 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.

Abstract translation: 一种封装在一起的堆叠微电子结构，其包括以翻转配置彼此附接的一对微电子封装。 在一个实施例中，封装在封装上的堆叠微电子结构可以包括第一和第二微电子封装，每个包括基板，其具有形成在每个微电子封装基板的第一表面上的至少一个封装连接焊盘， 电连接到每个微电子封装衬底第一表面的至少一个微电子器件，其中第一和第二微电子封装彼此连接，至少一个封装到封装的互连结构在第一微电子封装连接焊盘和 第二微电子封装连接焊盘。

公开(公告)号：US20160200566A1

公开(公告)日：2016-07-14

申请号：US14403571

申请日：2013-06-28

Applicant: INTEL IP CORPORATION

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

Abstract translation: 在实施例中，封装组件可以包括专用集成电路（ASIC）和具有有源侧和无源侧的微机电系统（MEMS）。 在实施例中，MEMS可以通过一个或多个互连直接耦合到ASIC。 MEMS，ASIC和一个或多个互连可以限定或形成空腔，使得MEMS的有源部分在空腔内。 在一些实施例中，封装组件可以包括通过多个一个或多个互连件直接耦合到ASIC的多个MEMS。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10903166B2

公开(公告)日：2021-01-26

申请号：US16060918

申请日：2016-01-28

Applicant: Sanka Ganesan ,  Thorsten Meyer ,  Gerald Ofner ,  Intel IP Corporation

Inventor： Sanka Ganesan ,  Thorsten Meyer ,  Gerald Ofner

IPC: H01L29/40 ,  H01L23/532 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Disclosed herein are integrated circuit (IC) packages, and related structures and techniques. In some embodiments, an IC package may include: a die; a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects and solder; a solder resist; and second-level interconnects coupled to the redistribution structure through openings in the solder resist.

公开(公告)号：US10301176B2

公开(公告)日：2019-05-28

申请号：US15857461

申请日：2017-12-28

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: B81B7/00 ,  B81C1/00

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US10228725B2

公开(公告)日：2019-03-12

申请号：US15282633

申请日：2016-09-30

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner

IPC: A44C5/00 ,  A44C5/02 ,  A44C5/10 ,  A45F5/00 ,  A61B5/00 ,  A61B5/11 ,  G06F1/16 ,  A61B5/021 ,  A61B5/024 ,  G04B37/14 ,  G04B47/00 ,  A61B5/0205 ,  H04B1/3827

Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.

公开(公告)号：US10211182B2

公开(公告)日：2019-02-19

申请号：US14649104

申请日：2014-07-07

Applicant: INTEL IP CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner

IPC: H01L23/48 ,  H01L21/60 ,  H01L25/065 ,  H01L25/10 ,  H01L21/54 ,  H01L25/00 ,  H05K1/11 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.

公开(公告)号：US09543224B1

公开(公告)日：2017-01-10

申请号：US14964494

申请日：2015-12-09

Applicant: INTEL IP CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Robert L. Sankman

IPC: H01L23/48 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/66 ,  H01L21/60

CPC classification number: H01L22/20 ,  H01L21/4853 ,  H01L21/568 ,  H01L22/12 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L24/76 ,  H01L24/96 ,  H01L24/97 ,  H01L2021/60292 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1421 ,  H01L2924/18162

Abstract: Semiconductor packages and methods, systems, and apparatuses of forming such packages are described. A method of forming a semiconductor package may include encapsulating a semiconductor die with a molding compound, applying a seed layer on the die and the molding compound, applying a resist layer on the seed layer, exposing a first portion of the resist layer, and exposing a second portion of the resist layer. The first portion can include a first area of the resist layer to be used for forming a redistribution layer (RDL) without including a second area of the resist layer to be used for forming an electrical communications pathway between at least one of the contact pads and the RDL. The second portion can include the second area of the resist layer that includes the electrical communications pathway.

Abstract translation: 描述了形成这种封装的半导体封装和方法，系统和装置。 形成半导体封装的方法可以包括用模塑料包封半导体管芯，在晶粒上施加种子层和模塑料，在种子层上施加抗蚀剂层，暴露抗蚀剂层的第一部分，并暴露 抗蚀剂层的第二部分。 第一部分可以包括用于形成再分布层（RDL）的抗蚀剂层的第一区域，而不包括用于在至少一个接触焊盘和至少一个接触焊盘之间形成电通信路径的抗蚀剂层的第二区域 RDL。 第二部分可以包括包括电通信路径的抗蚀剂层的第二区域。