公开(公告)号：US11777013B2

公开(公告)日：2023-10-03

申请号：US16457626

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Willy Rachmady ,  Van H. Le ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Matthew Metz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/45 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L29/66742 ,  H01L21/0262 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments herein describe techniques for a three dimensional transistor above a substrate. A three dimensional transistor includes a channel structure, where the channel structure includes a channel material and has a source area, a drain area, and a channel area between the source area and the drain area. A source electrode is coupled to the source area, a drain electrode is coupled to the drain area, and a gate electrode is around the channel area. An electrode selected from the source electrode, the drain electrode, or the gate electrode is in contact with the channel material on a sidewall of an opening in an inter-level dielectric layer or a surface of the electrode. The electrode is further in contact with the channel structure including the source area, the drain area, or the channel area. Other embodiments may be described and/or claimed.

公开(公告)号：US11527656B2

公开(公告)日：2022-12-13

申请号：US16141408

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Van H. Le ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Matthew Metz ,  Miriam Reshotko ,  Benjamin Chu-Kung ,  Shriram Shivaraman ,  Abhishek Sharma ,  Nazila Haratipour

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/24 ,  H01L29/66 ,  H01L27/108 ,  H01L29/45

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11508577B2

公开(公告)日：2022-11-22

申请号：US16024694

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/04 ,  H01L29/78 ,  H01L27/12

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199812A1

公开(公告)日：2022-06-23

申请号：US17129486

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Chelsey Dorow ,  Kevin O'Brien ,  Sudarat Lee ,  Kirby Maxey ,  Ashish Verma Penumatcha ,  Tanay Gosavi ,  Patrick Theofanis ,  Chia-Ching Lin ,  Uygar Avci ,  Matthew Metz ,  Shriram Shivaraman

IPC: H01L29/76 ,  H01L29/24 ,  H01L27/092 ,  H01L21/8256 ,  H01L21/02

Abstract: Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.

公开(公告)号：US11276694B2

公开(公告)日：2022-03-15

申请号：US16139684

申请日：2018-09-24

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew Metz ,  Gilbert Dewey ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/207

Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.

公开(公告)号：US11017843B2

公开(公告)日：2021-05-25

申请号：US16457617

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Gilbert Dewey ,  Willy Rachmady ,  Van Le ,  Matthew Metz ,  Jack Kavalieros

IPC: G11C11/24 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/12 ,  G11C11/4094 ,  G11C11/408

Abstract: In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.

公开(公告)号：US20200335610A1

公开(公告)日：2020-10-22

申请号：US16957667

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US20200312976A1

公开(公告)日：2020-10-01

申请号：US16363632

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Devin Merrill ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Owen Loh

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.

公开(公告)号：US10319646B2

公开(公告)日：2019-06-11

申请号：US15498280

申请日：2017-04-26

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC: B82Y10/00 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L27/092 ,  H01L29/205 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/8258

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US09947780B2

公开(公告)日：2018-04-17

申请号：US15229079

申请日：2016-08-04

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78 ,  G06F1/16 ,  G06F1/18 ,  H01L29/04 ,  H01L29/10 ,  H01L29/205 ,  H03F3/195 ,  H03F3/213 ,  H01L29/40 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.