公开(公告)号：WO2018034753A3

公开(公告)日：2018-02-22

申请号：PCT/US2017/041961

申请日：2017-07-13

Applicant: QUALCOMM INCORPORATED

Inventor： MUDAKATTE, Niranjan Sunil ,  BERDY, David Francis ,  YUN, Changhan Hobie ,  ZUO, Chengjie ,  GU, Shiqun ,  VELEZ, Mario Francisco ,  KIM, Jonghae

IPC: H05K1/16 ,  H01L49/02 ,  H03H7/01 ,  H03H7/46 ,  H05K1/03 ,  H03H1/00

Abstract: A passive device may include an inductor having interconnected trace segments. The passive device may also include parallel plate capacitors. Each of the plurality of parallel plate capacitors may have a dielectric layer between a pair of conductive plates. The parallel plate capacitors may not overlap more than one of the interconnected trace segments.

公开(公告)号：WO2018031213A1

公开(公告)日：2018-02-15

申请号：PCT/US2017/043127

申请日：2017-07-20

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Daeik Daniel ,  FU, Jie ,  ALDRETE, Manuel ,  KIM, Jonghae ,  YUN, Changhan Hobie ,  BERDY, David Francis ,  ZUO, Chengjie ,  VELEZ, Mario Francisco

IPC: H01L23/367 ,  H01L23/498

Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.

Abstract translation: 根据本公开的一些示例的半导体器件可以包括封装衬底，半导体管芯，其通过在半导体管芯的有源侧上的第一组接触连接到封装衬底的一侧，以及 在所述半导体管芯的背侧上与第二组接触件耦合到多个焊料印刷物。 半导体管芯可以包括将第一组触点连接到第二组触点的多个通孔，并且被配置为允许热量从管芯的活动侧传递到多个焊料印刷物以用于更短的散热路径。 / p>

公开(公告)号：WO2017200693A1

公开(公告)日：2017-11-23

申请号：PCT/US2017/028547

申请日：2017-04-20

Applicant: QUALCOMM INCORPORATED

Inventor： YUN, Changhan Hobie ,  ZUO, Chengjie ,  KIM, Daeik Daniel ,  VELEZ, Mario Francisco ,  MUDAKATTE, Niranjan Sunil ,  KIM, Jonghae ,  BERDY, David Francis

IPC: H01L23/522 ,  H01F17/00

CPC classification number: H01F27/40 ,  H01F17/00 ,  H01F27/2823 ,  H01F27/29 ,  H01F27/292 ,  H01F41/02 ,  H01F2017/002 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L28/10 ,  H03H7/0115 ,  H03H7/466

Abstract: An apparatus includes a substrate and a three-dimensional (3D) wirewound inductor integrated within the substrate. The apparatus further includes a capacitor coupled to the 3D wirewound inductor.

Abstract translation: 一种装置包括衬底和集成在衬底内的三维（3D）线绕电感器。 该设备还包括耦合到3D线绕电感器的电容器。

公开(公告)号：WO2017171991A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/014701

申请日：2017-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： YUN, Changhan Hobie ,  BERDY, David Francis ,  ZUO, Chengjie ,  KIM, Daeik Daniel ,  VELEZ, Mario Francisco ,  MUDAKATTE, Niranjan Sunil ,  MIKULKA, Robert Paul

IPC: H03H7/46

CPC classification number: H04B1/0057 ,  H01L2224/11 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  H03H2001/0085

Abstract: A three dimensional (3D) multiplexer structure may include a first two dimensional (2D) inductor capacitor (LC) filter layer. The first 2D LC filter layer may include a first 2D spiral inductor and a first capacitor(s). The 3D multiplexer structure may also include a second 2D LC filter layer. The second 2D LC filter layer may include a second 2D spiral inductor and a second capacitor(s) stacked directly on and communicably coupled to the first 2D LC filter.

Abstract translation: 三维（3D）多路复用器结构可以包括第一二维（2D）电感器电容器（LC）滤波器层。 第一2D LC滤波器层可以包括第一2D螺旋电感器和第一电容器。 3D多路复用器结构还可以包括第二2D LC滤波器层。 第二2DLC滤波器层可以包括直接堆叠在第一2DLC滤波器上并且可通信地耦合到第一2DLC滤波器的第二2D螺旋电感器和第二电容器。

公开(公告)号：WO2017165094A1

公开(公告)日：2017-09-28

申请号：PCT/US2017/020281

申请日：2017-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： MA, Yunfei ,  ZUO, Chengjie ,  BERDY, David ,  KIM, Daeik ,  YUN, Changhan ,  LAN, Je-Hsiung ,  VELEZ, Mario ,  MUDAKATTE, Niranjan Sunil ,  MIKULKA, Robert ,  KIM, Jonghae

IPC: H03H7/46 ,  H03H7/09

CPC classification number: H04B1/0057 ,  H03H7/09 ,  H03H7/463 ,  H04B1/04 ,  H04B1/3827 ,  H04B1/40 ,  H04B2001/0416 ,  H04L5/14

Abstract: An RF diplexer is provided with an integrated diplexer that shares a primary inductor included in a channel within the RF diplexer.

Abstract translation: RF双工器带有一个集成的双工器，共用一个包含在RF双工器内通道中的主电感器。

公开(公告)号：WO2017048379A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/044865

申请日：2016-07-29

Applicant: QUALCOMM INCORPORATED

Inventor： LAN, Je-Hsiung Jeffrey ,  MUDAKATTE, Niranjan Sunil ,  YUN, Changhan Hobie ,  KIM, Daeik Daniel ,  ZUO, Chengjie ,  BERDY, David Francis ,  VELEZ, Mario Francisco ,  KIM, Jonghae

IPC: H01L23/522

CPC classification number: H01L27/01 ,  H01L21/4846 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L28/10 ,  H01L28/75 ,  H01L2224/11

Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.

Abstract translation: 一种装置包括玻璃基板和电容器。 电容器包括耦合到第一电极的第一金属，电介质结构和包括电容器的第二电极的通孔结构。 第一金属结构通过电介质结构与通孔结构分离。

公开(公告)号：WO2017048369A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/044103

申请日：2016-07-26

Applicant: QUALCOMM INCORPORATED

Inventor： MUDAKATTE, Niranjan Sunil ,  KIM, Daeik Daniel ,  BERDY, David Francis ,  YUN, Changhan Hobie ,  LAN, Je-Hsiung Jeffrey ,  ZUO, Chengjie ,  VELEZ, Mario Francisco ,  MIKULKA, Robert Paul ,  KIM, Jonghae

IPC: H01L27/08 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L24/13 ,  H01L27/0805 ,  H01L28/87 ,  H01L28/91 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/94 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10337 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/03

Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.

Abstract translation: 增强电容器结构包括基板和在基板上的第一导电层的第一电容器板。 增强电容器结构还包括在第一电容器板的远离衬底的表面上的绝缘体层和第二电容器板。 第二电容器板包括在绝缘体层上的第二导电层，由第一电容器板作为第一电容器支撑。 与第一电容器串联耦合的第二电容器。 第一电容器板由第一电容器和第二电容器共享作为共用的第一电容器板。 扩展的第一电容器板包括第三导电层的第一虚拟部分和沿着共享的第一电容器板的表面延伸的第一虚设通孔条。 第一虚拟部分沿第一虚拟通孔条延伸并由第一虚拟通孔支撑。

公开(公告)号：WO2016048632A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/048632

申请日：2015-09-04

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Daeik Daniel ,  KIM, Jonghae ,  ZUO, Chengjie ,  PARK, Sang-June ,  YUN, Changhan Hobie ,  VELEZ, Mario Francisco ,  BERDY, David Francis ,  NOWAK, Matthew Michael ,  MIKULKA, Robert Paul

IPC: H01L21/768 ,  H01L27/08 ,  H01L29/94

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/94

Abstract: An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.

Abstract translation: 一种装置包括具有位于衬底的第一侧上的第一接触的变容二极管。 变容二极管包括位于衬底的第二侧上的第二接触件，第二侧面与第一侧相对。 该装置还包括在第一触点和第二触点之间的信号路径。

公开(公告)号：WO2015199936A1

公开(公告)日：2015-12-30

申请号：PCT/US2015/034220

申请日：2015-06-04

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Daeik Daniel ,  YUN, Changhan Hobie ,  VELEZ, Mario Francisco ,  ZUO, Chengjie ,  BERDY, David Francis ,  KIM, Jonghae

IPC: H01F17/00 ,  H01L49/02 ,  H01L23/64

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F41/04 ,  H01F2017/002 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/15 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  Y10T29/49075 ,  H01L2924/00

Abstract: Methods and apparatuses, wherein the method forms a first plurality of vias in a substrate, further comprising forming the first plurality of vias to be substantially the same height. The method forms a plurality of conductive traces external to the substrate and couples the plurality of conductive traces to the first plurality of vias: wherein the plurality of conductive traces and the first plurality of vias comprise a plurality of conductive turns and wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane.

Abstract translation: 方法和装置，其中所述方法在基底中形成第一多个通孔，还包括将所述第一多个通孔形成为基本上相同的高度。 该方法在衬底外部形成多个导电迹线，并将多个导电迹线耦合到第一多个通孔：其中多个导电迹线和第一多个通孔包括多个导电匝，并且其中多个导电 匝在基本上在第一平面内的螺旋构造。

公开(公告)号：WO2015134324A1

公开(公告)日：2015-09-11

申请号：PCT/US2015/018057

申请日：2015-02-27

Applicant: QUALCOMM INCORPORATED

Inventor： YUN, Changhan Hobie ,  ZUO, Chengjie ,  KIM, Jonghae ,  VELEZ, Mario Francisco ,  KIM, Daeik Daniel ,  WILCOX, Rick Allen

IPC: H03H9/02 ,  H03H9/13

CPC classification number: H03H9/02448 ,  H03H3/02 ,  H03H9/02133 ,  H03H9/02228 ,  H03H9/02244 ,  H03H9/132 ,  H03H9/133 ,  H03H9/15 ,  H03H9/462 ,  H03H9/54 ,  H03H2003/027

Abstract: An integrated circuit device (300) includes a piezoelectric substrate (302) having a first surface and a second surface opposite the first surface. The device also includes a first electrode (304) and a second electrode (306) on the first surface of the piezoelectric substrate, the first electrode (304) having a first width (314) and the second electrode (306) having a second width (316). The device further includes a third electrode (308) and a fourth electrode (310) on the second surface of the piezoelectric substrate, the third electrode (308) having a third width (318) that is substantially the same as the second width (316), and the fourth electrode (310) having a fourth width (320) that is substantially the same as the first width (314). The first and third electrodes operate as part of a first portion of a microelectromechanical systems (MEMS) resonator, and the second and fourth electrodes operate as part of a second portion of the MEMS resonator.

Abstract translation: 集成电路器件（300）包括具有第一表面和与第一表面相对的第二表面的压电基片（302）。 该装置还包括在压电基片的第一表面上的第一电极（304）和第二电极（306），第一电极（304）具有第一宽度（314），第二电极（306）具有第二宽度 （316）。 该装置还包括在压电基片的第二表面上的第三电极（308）和第四电极（310），第三电极（308）具有与第二宽度（316）基本相同的第三宽度 ），并且第四电极（310）具有与第一宽度（314）基本相同的第四宽度（320）。 第一和第三电极作为微机电系统（MEMS）谐振器的第一部分的一部分工作，第二和第四电极作为MEMS谐振器的第二部分的一部分工作。