公开(公告)号：WO2018044543A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/046793

申请日：2017-08-14

Applicant: QUALCOMM INCORPORATED

Inventor： VELEZ, Mario ,  MUDAKATTE, Niranjan Sunil ,  YUN, Changhan ,  BERDY, David ,  GU, Shiqun ,  KIM, Jonghae ,  ZUO, Chengjie

IPC: H01L23/64 ,  H02M3/00

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L28/10 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to operate as at least one passive component, a first die coupled to the single substrate layer and the plurality of interconnects, and an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component. In some implementations, the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μm) or less. In some implementations, the single substrate layer comprises a thickness of about 75 microns (μm) or less.

Abstract translation: 包括单个衬底层，在单个衬底层上的多个互连，多个互连配置为作为至少一个无源部件操作的器件，耦合到单个衬底层的第一管芯 所述多个互连以及至少部分地封装所述第一管芯和所述多个互连的封装层，所述封装层被配置为作为至少一个无源组件进行操作。 在一些实施方式中，单个衬底层，第一管芯和封装层包括约225微米（μm）或更小的总厚度。 在一些实施方式中，单个基底层包括约75微米（μm）或更小的厚度。

公开(公告)号：WO2018038915A1

公开(公告)日：2018-03-01

申请号：PCT/US2017/045982

申请日：2017-08-08

Applicant: QUALCOMM INCORPORATED

Inventor： YUN, Changhan Hobie ,  LAN, Je-Hsiung ,  ZUO, Chengjie ,  BERDY, David ,  KIM, Jonghae ,  VELEZ, Mario ,  MUDAKATTE, Niranjan Sunil ,  GU, Shiqun

IPC: H03H3/04 ,  H03H9/17

CPC classification number: H03H9/205 ,  H01L41/332 ,  H03H3/04 ,  H03H9/173 ,  H03H9/54 ,  H03H2003/021 ,  H03H2003/0435 ,  H03H2003/0442 ,  H03H2003/0471

Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device (200) includes multiple FBARs (202, 204, 206) having different resonant frequencies formed over a single substrate (220). The FBARs include piezoelectric layers (212, 214, 216) having different thicknesses but with upper electrodes (218) formed at a same height over the substrate, lower electrodes (210) at different heights over the substrate, and different sized air gaps (224, 226, 228) separating the lower electrodes from the substrate.

Abstract translation: 单芯片多FBAR（薄膜体声波谐振器）装置（200）包括在单个衬底（220）上形成的具有不同谐振频率的多个FBAR（202,204,206）。 FBAR包括具有不同厚度的压电层（212,214,216），但是具有在衬底上方以相同高度形成的上电极（218），在衬底上的不同高度处的下电极（210）以及不同尺寸的气隙（224 ，226,228）将下电极与衬底分开。

公开(公告)号：WO2017165094A1

公开(公告)日：2017-09-28

申请号：PCT/US2017/020281

申请日：2017-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： MA, Yunfei ,  ZUO, Chengjie ,  BERDY, David ,  KIM, Daeik ,  YUN, Changhan ,  LAN, Je-Hsiung ,  VELEZ, Mario ,  MUDAKATTE, Niranjan Sunil ,  MIKULKA, Robert ,  KIM, Jonghae

IPC: H03H7/46 ,  H03H7/09

CPC classification number: H04B1/0057 ,  H03H7/09 ,  H03H7/463 ,  H04B1/04 ,  H04B1/3827 ,  H04B1/40 ,  H04B2001/0416 ,  H04L5/14

Abstract: An RF diplexer is provided with an integrated diplexer that shares a primary inductor included in a channel within the RF diplexer.

Abstract translation: RF双工器带有一个集成的双工器，共用一个包含在RF双工器内通道中的主电感器。

公开(公告)号：EP3433930A1

公开(公告)日：2019-01-30

申请号：EP17712881.6

申请日：2017-03-01

Applicant: Qualcomm Incorporated

Inventor： MA, Yunfei ,  ZUO, Chengjie ,  BERDY, David ,  KIM, Daeik ,  YUN, Changhan ,  LAN, Je-Hsiung ,  VELEZ, Mario ,  MUDAKATTE, Niranjan Sunil ,  MIKULKA, Robert ,  KIM, Jonghae

IPC: H03H7/46 ,  H03H7/09

公开(公告)号：WO2018017246A1

公开(公告)日：2018-01-25

申请号：PCT/US2017/038363

申请日：2017-06-20

Applicant: QUALCOMM INCORPORATED

Inventor： YUN, Changhan ,  ZUO, Chengjie ,  VELEZ, Mario ,  MUDAKATTE, Niranjan Sunil ,  GU, Shiqun ,  KIM, Jonghae ,  BERDY, David

IPC: H01L23/522 ,  H01L23/64 ,  H01L21/60 ,  H05K1/16 ,  H05K1/18 ,  H05K3/46 ,  H01F17/00 ,  H04B1/00

CPC classification number: H04B1/1638 ,  H01F17/0013 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/64 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L27/01 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2223/6688 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H04B1/006 ,  H05K1/165 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/097 ,  H05K2201/09827

Abstract: In an illustrative example, an apparatus (100) includes a passive-on-glass (POG) device (104) integrated within a glass substrate (102). The apparatus further includes a semiconductor die (106) integrated within the glass substrate.

Abstract translation: 在说明性示例中，装置（100）包括集成在玻璃衬底（102）内的玻璃上被动式（POG）器件（104）。 该设备还包括集成在玻璃衬底内的半导体芯片（106）。

公开(公告)号：WO2017161199A1

公开(公告)日：2017-09-21

申请号：PCT/US2017/022829

申请日：2017-03-16

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Daeik ,  FU, Jie ,  YUN, Changhan ,  KIM, Chin-Kwan ,  ALDRETE, Manuel ,  ZUO, Chengjie ,  VELEZ, Mario ,  KIM, Jonghae

IPC: H01L23/538 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

Abstract translation: 提供了一种装置和制造方法。 该装置包括具有第一侧和相对的第二侧的基板，限定在基板内从第一侧开始的空腔，耦合到空腔的底板并且在远离地板的管芯侧上具有导电垫的管芯 的空腔。 可以包括耦合到衬底的第二侧的层压层。 一次可以钻出一个孔，穿过器件的各层，穿过模具，并穿过导电垫。 该孔延伸穿过并被限定在层压层（如果存在）内，衬底的第二侧，管芯和导电垫内。 导电材料设置在孔内并且在层压层（如果提供的话），衬底的第二侧，管芯和导电垫之间并穿过层压层延伸。

公开(公告)号：EP3488467A1

公开(公告)日：2019-05-29

申请号：EP17735704.3

申请日：2017-06-20

Applicant: Qualcomm Incorporated

Inventor： YUN, Changhan ,  ZUO, Chengjie ,  VELEZ, Mario ,  MUDAKATTE, Niranjan Sunil ,  GU, Shiqun ,  KIM, Jonghae ,  BERDY, David

IPC: H01L23/522 ,  H01L23/64 ,  H01L21/60 ,  H05K1/16 ,  H05K1/18 ,  H05K3/46 ,  H01F17/00 ,  H04B1/00