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    32.
    发明专利
    未知

    公开(公告)号：FR2732151B1

    公开(公告)日：1997-04-25

    申请号：FR9503294

    申请日：1995-03-21

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： SOURGEN LAURENT ,  WUIDART SYLVIE

    IPC: G11C17/00 ,  G11C7/00 ,  G11C16/02 ,  G11C16/22 ,  G06K19/07

    Abstract: The method involves using a high-voltage generator (1) and regulator (2) delivering the write pulse (Ve) to the memory address decoder (5) in response to a command (3) from a counter (9) initialised by a pseudo-random number generator (8). A microprocessor ( mu p) decodes a write instruction received via input/output signals (IO1,IO2) and reads the random number which is decremented to 1 at the rate of the clock (Clk). A constant delay between the external write command and the end-of-write signal is held in a memory (10) which activates another counter (11) and is programmed for each circuit.

    33.
    发明专利
    未知

    公开(公告)号：DE69301795T2

    公开(公告)日：1996-07-25

    申请号：DE69301795

    申请日：1993-07-15

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： LISART MATHIEU ,  SOURGEN LAURENT

    IPC: G06F3/08 ,  G06F12/00 ,  G06F12/02 ,  G06F12/14 ,  G06F21/02 ,  G06K19/073 ,  G07F7/10 ,  G11C7/24 ,  G11C8/04 ,  G11C16/02 ,  G11C17/00 ,  G11C7/00

    Abstract: In a memory, an area descriptor contains authorizations of action which may be reading, writing and erasure and which pertain to words in memory of an area of the memory controlled by this descriptor. This area descriptor also includes an information item regarding the length of the memory area in the form of the address of a next descriptor. An internal signal for area checking is produced for the purpose of storing on the one hand a mode of managing the memory area and on the other hand an address corresponding to the end of area. Subsequently, the end-of-area address is compared with the addresses output by an address counter. A modification of this storage is effected on arriving at the end of an area, at the start of a following area beginning with the descriptor of this following area.

    34.
    发明专利
    未知

    公开(公告)号：DE69301795D1

    公开(公告)日：1996-04-18

    申请号：DE69301795

    申请日：1993-07-15

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： LISART MATHIEU ,  SOURGEN LAURENT

    IPC: G06F3/08 ,  G06F12/00 ,  G06F12/02 ,  G06F12/14 ,  G06F21/02 ,  G06K19/073 ,  G07F7/10 ,  G11C7/24 ,  G11C8/04 ,  G11C16/02 ,  G11C17/00 ,  G11C7/00

    Abstract: In a memory, an area descriptor contains authorizations of action which may be reading, writing and erasure and which pertain to words in memory of an area of the memory controlled by this descriptor. This area descriptor also includes an information item regarding the length of the memory area in the form of the address of a next descriptor. An internal signal for area checking is produced for the purpose of storing on the one hand a mode of managing the memory area and on the other hand an address corresponding to the end of area. Subsequently, the end-of-area address is compared with the addresses output by an address counter. A modification of this storage is effected on arriving at the end of an area, at the start of a following area beginning with the descriptor of this following area.

    37.
    发明专利
    未知

    公开(公告)号：FR2694120B1

    公开(公告)日：1994-09-23

    申请号：FR9209195

    申请日：1992-07-24

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： LISART MATHIEU ,  SOURGEN LAURENT

    IPC: G06F3/08 ,  G06F12/00 ,  G06F12/02 ,  G06F12/14 ,  G06F21/02 ,  G06K19/073 ,  G07F7/10 ,  G11C7/24 ,  G11C8/04 ,  G11C16/02 ,  G11C17/00 ,  G11C16/00 ,  G06K19/07

    Abstract: In a memory, an area descriptor contains authorizations of action which may be reading, writing and erasure and which pertain to words in memory of an area of the memory controlled by this descriptor. This area descriptor also includes an information item regarding the length of the memory area in the form of the address of a next descriptor. An internal signal for area checking is produced for the purpose of storing on the one hand a mode of managing the memory area and on the other hand an address corresponding to the end of area. Subsequently, the end-of-area address is compared with the addresses output by an address counter. A modification of this storage is effected on arriving at the end of an area, at the start of a following area beginning with the descriptor of this following area.

    38.
    发明专利
    未知

    公开(公告)号：DE69000133T2

    公开(公告)日：1993-01-07

    申请号：DE69000133

    申请日：1990-12-06

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： SOURGEN LAURENT

    IPC: G11C16/30 ,  G11C17/16 ,  H01L23/525 ,  H03K17/10 ,  G11C16/06 ,  G11C16/04

    Abstract: MOS blow-out fuse with programmable tunnel oxide. Such a fuse is composed of a tunnel oxide EEPROM memory cell, and of an EEPROM memory plane whose tunnel oxide can, at a given moment of the application, be blown by switching a steep front in place of a slow front of a program/erase voltage Vpp. Such a fuse can be used in all MOS integrated circuits, and is addressed in particular at applications of memory-card type. … …

    39.
    发明专利
    未知

    公开(公告)号：FR2623651B1

    公开(公告)日：1992-11-27

    申请号：FR8716063

    申请日：1987-11-20

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： DEVIN JEAN ,  SOURGEN LAURENT ,  GILLE

    IPC: G11C14/00 ,  G11C11/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    Abstract: In order to avoid technological differentiation between random- access memory cells and read-only memory cells of a single memory plane, all the memory cells are produced with a single technology. These memory cells are then essentially composed of floating-gate transistors. Programming of the random-access memory cells is done, conventionally, by injecting, or not, electronic charges into the floating gates of the transistors. The programming (IM, Im), or not, of the read-only memory cells is done by implanting impurities (^I) into the conduction channels of the floating-gate transistors of these memory cells. It is shown that concealment is improved of the contents of the read-only memory cells which contents are intended to remain hidden, whilst improving the conditions for producing prototypes on request. … …

    40.
    发明专利
    未知

    公开(公告)号：FR2623650A1

    公开(公告)日：1989-05-26

    申请号：FR8716062

    申请日：1987-11-20

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： SOURGEN LAURENT ,  LISIMAQUE GILLES

    IPC: G06F12/06 ,  G06F15/78 ,  G11C11/00 ,  G11C16/04 ,  G11C17/00

    Abstract: A monolithic electronic component is produced whilst saving space on the semiconductor substrate. The space saved (16) results from the allocating of a single decoder (9-10) to a mixed memory plane comprising read-only memory cells (4) and programmable memory cells (5). When, for various reasons, it is necessary to arrange a communication between the memory space containing the read-only memories and the memory space comprising the programmable memories, the information content, wholly or partly, of the read-only memories is transferred (11) into the processing memory of the monolithic electronic circuit. It is shown that space is thereby saved in this circuit by reducing the size of the access decoders.

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