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    31.
    发明专利
    未知

    公开(公告)号：DE69527146T2

    公开(公告)日：2002-12-12

    申请号：DE69527146

    申请日：1995-11-10

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： FRISINA FERRUCCIO

    IPC: H01L27/02 ,  H01L29/78

    Abstract: The device (10) presents a polysilicon layer (36) extending over a wafer (20) of semiconductor material, along the edge of the active region (34) of the device, and partly over a thick field oxide layer (35) which externally delimits the active region. The polysilicon layer (36) forms both a field-plate region (37) at its inner edge, and a Zener protection diode (11) over the field oxide layer (35), outwards of and contiguous to the field-plate region (37). The terminals of the diode (11) are respectively connected to the source metal region (30) and the gate metal region (44); the diode (11) therefore extends along the whole of the perimeter of the device (10), and presents an extensive junction area without greatly reducing the active area of the device.

    32.
    发明专利
    未知

    公开(公告)号：DE69527146D1

    公开(公告)日：2002-07-25

    申请号：DE69527146

    申请日：1995-11-10

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： FRISINA FERRUCCIO

    IPC: H01L27/02 ,  H01L29/78

    Abstract: The device (10) presents a polysilicon layer (36) extending over a wafer (20) of semiconductor material, along the edge of the active region (34) of the device, and partly over a thick field oxide layer (35) which externally delimits the active region. The polysilicon layer (36) forms both a field-plate region (37) at its inner edge, and a Zener protection diode (11) over the field oxide layer (35), outwards of and contiguous to the field-plate region (37). The terminals of the diode (11) are respectively connected to the source metal region (30) and the gate metal region (44); the diode (11) therefore extends along the whole of the perimeter of the device (10), and presents an extensive junction area without greatly reducing the active area of the device.

    33.
    发明专利
    未知

    公开(公告)号：DE69428894T2

    公开(公告)日：2002-04-25

    申请号：DE69428894

    申请日：1994-08-02

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L29/78 ,  H01L29/739

    Abstract: A power device integrated structure comprises a semiconductor substrate (5) of a first conductivity type, a semiconductor layer (3,4) of a second conductivity type superimposed over said substrate (5), a plurality of first doped regions (2) of the first conductivity type formed in the semiconductor layer (3,4), and a respective plurality of second doped regions (11) of the second conductivity type formed inside the first doped regions (2); the power device comprises: a power MOSFET (M) having a first electrode region represented by the second doped regions (11) and a second electrode region represented by the semiconductor layer (3,4); a first bipolar junction transistor (T2) having an emitter, a base and a collector respectively represented by the substrate (5), the semiconductor layer (3,4) and the first doped regions (2); and a second bipolar junction transistor (T1) having an emitter, a base and a collector respectively represented by the second doped regions (11), the first doped regions (2) and the semiconductor layer (3,4); the doping profiles of the semiconductor substrate (5), the semiconductor layer (3,4), the first doped regions (2) and the second doped regions (11) are such that the first and second bipolar junction transistors (T2,T1) have respective first and second common base current gains sufficiently high to cause said bipolar junction transistors to be biased in the high injection region, so that carriers are injected from the substrate (5) into the semiconductor layer (3,4) and from the second doped regions (11), through the first doped regions (2), into the semiconductor layer (3,4), the conductivity of the semiconductor layer (3,4) is thus modulated not only by the injection of minority carriers from the substrate (5), but also by majority carriers injected from the doped regions (11) into the first doped regions (2) and collected by the semiconductor layer (3,4). The first and second common base current gains summed are less than unity to prevent a parasitic thyristor from triggering on. The power device functions as an IGBT, having a reduced on-state voltage.

    35.
    发明专利
    未知

    公开(公告)号：DE69434268T2

    公开(公告)日：2006-01-12

    申请号：DE69434268

    申请日：1994-07-14

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

    Abstract: A high-speed MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a lightly doped semiconductor layer (1) of a first conductivity type, the elementary functional units comprising channel regions (6) of a second conductivity type covered by a conductive insulated gate layer (8) comprising a polysilicon layer (5); the conductive insulated gate layer (8) also comprises a highly conductive layer (9) superimposed over said polysilicon (5) layer and having a resistivity much lower than the resistivity of the polysilicon layer (5), so that a resistance introduced by the polysilicon layer (5) is shunted with a resistance introduced by said highly conductive layer (9) and the overall resistivity of the conductive insulated gate (8) layer is lowered.

    36.
    发明专利
    未知

    公开(公告)号：DE69533134T2

    公开(公告)日：2005-07-07

    申请号：DE69533134

    申请日：1995-10-30

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739

    Abstract: A MOS technology power device comprises a plurality of elementary functional units which contribute for respective fractions to an overall current of the power device and which are formed in a semiconductor material layer (2) of a first conductivity type. Each elementary functional unit comprises a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of a body stripe (3) elongated in a longitudinal direction on a surface of the semiconductor material layer (2). Each body stripe (3) includes at least one source portion (60) doped with dopants of the first conductivity type which is intercalated with a body portion (40) of the body stripe (3) wherein no dopants of the first conductivity type are provided.

    37.
    发明专利
    未知

    公开(公告)号：DE69531783T2

    公开(公告)日：2004-07-15

    申请号：DE69531783

    申请日：1995-10-09

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： FRANCO GIOVANNI ,  CAMALLERI CATENO MARCO ,  FRISINA FERRUCCIO

    IPC: H01L21/761 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06

    Abstract: A construction method for power devices with deep edge ring, which has the particularity of comprising the following steps: (a) the growth of a lightly doped N-type epitaxial layer (20) on a heavily doped N-type substrate (10); (b) the growth of an oxide (30) on the upper portion of the epitaxial layer (20); (c) the masked implantation of boron ions (40); (d) an oxide etching to expose regions for aluminum ion implantation; (e) the growth of a layer of preimplantation oxide; (f) the masking of the body regions with a layer of photosensitive material (50) and the implantation of aluminum ions (60); and (g) a single thermal diffusion process for forming a layer of thermal oxide (70) above the epitaxial layer (20) and for simultaneously forming at least one deep aluminum ring (90) that is adjacent to the body region doped with boron (80).

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