-
公开(公告)号：FR2791155B1
公开(公告)日：2001-05-11
申请号：FR9903407
申请日：1999-03-17
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN
Abstract: A coprocessor includes a single multiplication circuit coupled to a computation circuit dedicated to the computation of Y0, with Y0=(X*J0) mod 2 and J0 being defined by the equation ((N*J0)+1) mod 2 =0. A method also computes a modular operation using the circuit for the computation of Y0. The computation circuit computes Y0 on the basis, first, of the k least significant bits of a data element X=S(i-1)+(Ai*B) provided by an accumulator and, second, of the least significant word of N contained in a latch.
-
公开(公告)号：FR2791157A1
公开(公告)日：2000-09-22
申请号：FR9903410
申请日：1999-03-17
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN
Abstract: The circuit comprises a coprocessor (200) for effecting modular operations according to Montgomery's methods. The coprocessor has a single multiplication accumulator circuit (231). An Independent claim is made for a procedure for carrying out a modular operation using Montgomery's method.
-
公开(公告)号：FR2788865A1
公开(公告)日：2000-07-28
申请号：FR9900988
申请日：1999-01-27
Applicant: ST MICROELECTRONICS SA
Inventor： PLESSIER BERNARD , POMET ALAIN
Abstract: A first k bit shift register (150) has a parallel input and a series output. The parallel input is connected to an input of a first flip-flop circuit (155). A second k bit flip-flop circuit (159) has a parallel input and a parallel output. The latter is connected to a data bus (161). A second k bit shift register (154) has a serial input and a parallel output. The latter is connected to the input of the flip-flop circuit (159). An Independent claim is included for: (a) a coprocessor
-
公开(公告)号：DE602006009447D1
公开(公告)日：2009-11-12
申请号：DE602006009447
申请日：2006-07-12
Applicant: ST MICROELECTRONICS SA
Inventor： DUVAL BENJAMIN , POMET ALAIN
IPC: G06F13/40
Abstract: The peripheral has an interface circuit with a detection circuit (DCT) detecting the presence or absence of pull-down resistors of a master device (H) e.g. computer. The circuit (DCT) is connected to positive and negative data terminals (D+, D-) of a universal serial bus (USB) port of the peripheral. The peripheral establishes a communication with the device (H) via the port, if the circuit (DCT) detects the resistors. The circuit (DCT) verifies if voltages applied to the data terminals exceed 0.8 volts, if DC voltages (Vg+, Vg-, Vg) provided by a generator (VGEN) is less than 0.8 volts.
-
公开(公告)号：DE60040380D1
公开(公告)日：2008-11-13
申请号：DE60040380
申请日：2000-12-20
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN
IPC: H03K3/3562 , G06K19/073 , H03K3/037
Abstract: A master-slave D type flip-flop circuit includes a power consumption masking circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.
-
Patent Agency Ranking
公开(公告)号：FR2896057A1
公开(公告)日：2007-07-13
申请号：FR0600251
申请日：2006-01-12
Applicant: ST MICROELECTRONICS SA , AXALTO SA
Inventor： POMET ALAIN , DUVAL BENJAMIN , LEYDIER ROBERT
Abstract: L'invention concerne un procédé de génération d'un nombre aléatoire, comprenant des étapes de réception d'un signal binaire (RxD) de transmission de données soumis à une fluctuation de phase, de génération de plusieurs signaux d'oscillateur (P0-P7) sensiblement de même fréquence moyenne et ayant des phases respectives distinctes, de prélèvement d'un état (S0-S7) de chacun des signaux d'oscillateur à l'apparition de fronts du signal binaire (RxD), et d'élaboration d'un nombre aléatoire (RND) à partir des états de chacun des signaux d'oscillateur. Application à un circuit intégré utilisable dans une carte à puce.
-
公开(公告)号：DE60128608D1
公开(公告)日：2007-07-12
申请号：DE60128608
申请日：2001-01-24
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN , MALHERBE ALEXANDRE , MARINET FABRICE
Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.
-
公开(公告)号：FR2887351A1
公开(公告)日：2006-12-22
申请号：FR0551649
申请日：2005-06-16
Applicant: ST MICROELECTRONICS SA
Inventor： TEGLIA YANNICK , LIARDET PIERRE YVAN , POMET ALAIN
IPC: G06F12/14
Abstract: L'invention concerne un procédé et un circuit de protection d'une quantité numérique (d) contenue dans un circuit intégré (1) sur un premier nombre de bits (n), dans un calcul d'exponentiation modulaire d'une donnée (M) par ladite quantité numérique, consistant à : sélectionner au moins un deuxième nombre (j) compris entre l'unité et ledit premier nombre moins deux ; diviser ladite quantité numérique en au moins deux parties, une première partie (d(j-1, 0)) comprenant, depuis le bit de rang nul, un nombre de bits égal audit deuxième nombre, une deuxième partie (d(n-1, j)) comprenant les bits restants ; pour chaque partie de la quantité, calculer une première exponentiation modulaire (32, 33) de ladite donnée par la partie concernée et une deuxième exponentiation modulaire (36, 34) du résultat de la première par le chiffre 2 élevé à la puissance du rang du premier bit de la partie concernée ; et calculer (35) le produit des résultats des deuxièmes exponentiations modulaires.
-
公开(公告)号：FR2801751B1
公开(公告)日：2002-01-18
申请号：FR9915115
申请日：1999-11-30
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN , PLESSIER BERNARD , SOURGEN LAURENT
Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.
-
公开(公告)号：FR2788865B1
公开(公告)日：2001-10-05
申请号：FR9900988
申请日：1999-01-27
Applicant: ST MICROELECTRONICS SA
Inventor： PLESSIER BERNARD , POMET ALAIN
-
-
-
-
-
-
-
-
-
Search Results
43
records
(took 0.022 seconds)
