公开(公告)号：DE60000111T2

公开(公告)日：2002-10-31

申请号：DE60000111

申请日：2000-01-06

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  MONIER GUY ,  LEPAREUX MARIE-NOELLE

IPC: G06F7/52 ,  G06F7/72

Abstract: The multiplier circuit forms part of a mathematical generator assembly and has three input adders (14-17) series cascade connected with bistable connection circuits (7-9) and with bistable input connections (10-13). There is a nulling circuit (18) which prevents the operation of the input and output two bistable circuits (10,13) allowing operation within the mathematical generator assembly.

公开(公告)号：FR2820577A1

公开(公告)日：2002-08-09

申请号：FR0101684

申请日：2001-02-08

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  TEGLIA YANNICK

IPC: G09C1/00 ,  H04L9/06 ,  H04L9/08

Abstract: The invention concerns a secure method for cryptographic calculation to supply an output (MS) from an input (ME) and a secret key (K0), the method comprising several key calculating steps (ET2), each supplying an updated derivative key (M'1, M'2) from a derivative key previously calculated in accordance with a known key calculating law, the first updated derivative key (M'1) being obtained from the secret key (K0). The invention is characterised in that the method further comprises a masking step (ET1) carried out prior to a first key calculating step (ET2), to mask the secret key (K0) so that the updated derivative key (M'1, M'i) is different at each implementation of the method. The invention is applicable to banking transactions, or more generally secure transfer operations.

公开(公告)号：FR2820576A1

公开(公告)日：2002-08-09

申请号：FR0101685

申请日：2001-02-08

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  TEGLIA YANNICK

IPC: G09C1/00 ,  H04L9/06

Abstract: The invention concerns a secure cryptographic method comprising N cycles of calculation successively carried out to obtain an output from an input and a secret key. The invention is characterised in that it consists in: producing a first masking level to mask the input so that each data used or produced by a cycle of calculation should be masked, and producing a second masking level to mask data manipulated within each cycle of calculation. The invention also concerns an electronic component using such a method. The invention is particularly interesting for banking transactions or more generally secure transfer operations.

公开(公告)号：DE69900306T2

公开(公告)日：2002-07-04

申请号：DE69900306

申请日：1999-02-17

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE

IPC: G06F7/52 ,  G06F7/544 ,  G06F7/72

公开(公告)号：DE60000111D1

公开(公告)日：2002-05-16

申请号：DE60000111

申请日：2000-01-06

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  MONIER GUY ,  LEPAREUX MARIE-NOELLE

IPC: G06F7/52 ,  G06F7/72

Abstract: The multiplier circuit forms part of a mathematical generator assembly and has three input adders (14-17) series cascade connected with bistable connection circuits (7-9) and with bistable input connections (10-13). There is a nulling circuit (18) which prevents the operation of the input and output two bistable circuits (10,13) allowing operation within the mathematical generator assembly.

公开(公告)号：FR2790347A1

公开(公告)日：2000-09-01

申请号：FR9902364

申请日：1999-02-25

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE

IPC: G06F12/14 ,  G06F21/55 ,  G06F21/85 ,  G06K19/10 ,  H04L9/28 ,  H04L12/22 ,  H04L9/00

Abstract: The invention concerns a method for making secure a sequence of working operations, of the same type, performed by an electronic circuit in the execution of an algorithm. The method is characterised in that it comprises a step which consists in introducing randomly one or several dummy operations in the sequence of operations, so as to prevent fraudulent access, by statistical analysis of electric currents, to protected data.