公开(公告)号：DE69602984D1

公开(公告)日：1999-07-29

申请号：DE69602984

申请日：1996-03-06

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: G06F12/14 ,  G11C8/20 ,  G11C16/02 ,  G11C17/00 ,  G11C8/00

Abstract: The address determined by the structure of the memory (ADF) or (ADFM) may be taken as the last address in the memory. The user commences writing sensitive information into the memory (MM) at an address of his choice (ADP) stored in a register (RV) and protected by a monostable (FW). The user entry ends at the structurally determined address (ADF) which activates a sequencer (SEQ1), a curtain (FL) and transfers the chosen address (ADP) into a non volatile register (RNV) establishing partition. A comparator (COMP) checks that subsequent addresses do not lie in the protected zone and inhibits the write authorisation (WE) if they do.

公开(公告)号：DE69601976D1

公开(公告)日：1999-05-12

申请号：DE69601976

申请日：1996-05-29

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: G11C16/12 ,  H03K4/02 ,  G11C16/06

Abstract: The generator includes a sampling circuit (S20,S22) which receives an input voltage and generates a sampled voltage. The sampled voltage and the generator output are added to produce a new voltage which is greater than the input voltage. A transmission or voltage follower circuit receives the new voltage and the real generator output to obtain a new generator output. The voltage follower circuit includes a first switch with an input terminal coupled to the voltage follower output terminal and a base terminal of the switch. A first capacitor is coupled to the base terminal and a reference voltage. A second switch has a first terminal coupled to a voltage follower circuit input and a third common terminal coupled to a first plate of a second capacitor. A third switch has a first terminal coupled the a reference voltage and a second terminal coupled to the base terminal. A common terminal is linked to the second plate of the second capacitor. The third capacitor is coupled to the second switch second terminal and the reference voltage.

公开(公告)号：FR2903205A1

公开(公告)日：2008-01-04

申请号：FR0605814

申请日：2006-06-28

Applicant: ST MICROELECTRONICS SA

Inventor： MURILLO LAURENT ,  TAILLIET FRANCOIS

IPC: G06F1/14 ,  H03K19/003 ,  H03K19/177

Abstract: L'invention concerne un procédé de protection d'une machine d'état (FSM) ayant un fonctionnement modélisé par un ensemble d'états reliés entre eux par des transitions, la machine d'état évaluant à chaque transition durant une phase d'évaluation des signaux de sortie (PO, SO) en fonction de signaux d'entrée (PI, SI) comprenant des signaux (PI) évalués lors d'une transition précédente, le procédé comprenant des étapes de détermination d'une durée minimale de chaque phase d'évaluation en fonction d'une durée minimale nécessaire à l'évaluation des signaux de sortie (PO, SO) en fonction des signaux d'entrée (PI, SI ) , et d'ajustement de la durée de chaque phase d'évaluation.

公开(公告)号：DE69428480D1

公开(公告)日：2001-11-08

申请号：DE69428480

申请日：1994-05-25

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  TAILLIET FRANCOIS

IPC: H01L21/8234 ,  H01L27/07 ,  H01L27/088 ,  H03B5/20 ,  H03K3/0231 ,  H03K3/86 ,  H03B5/24

公开(公告)号：DE69606968D1

公开(公告)日：2000-04-13

申请号：DE69606968

申请日：1996-12-24

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: H02M3/07

公开(公告)号：FR2879338A1

公开(公告)日：2006-06-16

申请号：FR0413248

申请日：2004-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： DELSUC BERTRAND ,  TAILLIET FRANCOIS

IPC: G11C16/12

Abstract: L'invention concerne une cellule mémoire (CEijk) comprenant un transistor d'accès (AT) et un transistor à grille flottante (FGTE), le transistor à grille flottante comportant une grille de contrôle (42), une région de drain (40) reliée à une région de source (11) du transistor d'accès, une grille flottante (43) et une fenêtre tunnel (TW). Selon l'invention, la cellule mémoire comprend un transistor de contrôle (CT) distinct du transistor d'accès, la grille flottante (43) comprend une extension (43-3) s'étendant en regard de la région de source (51) du transistor de contrôle, et la fenêtre tunnel (TW) est agencée entre l'extension (43-3) de la grille flottante (43) et la région de source du transistor de contrôle. En phase de programmation, un potentiel électrique d'effacement ou de programmation de la cellule mémoire est appliqué sur la région de drain (50) du transistor de contrôle, par l'intermédiaire de sa région de source (51). Avantages : suppression du stress de programmation du transistor à grille flottante.

公开(公告)号：FR2858725B1

公开(公告)日：2005-10-07

申请号：FR0309680

申请日：2003-08-06

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: H02M3/07

Abstract: A generator produces a high voltage from a power supply voltage. The generator includes an oscillator for producing a driving signal, and a charge pump for producing the high voltage from the power supply voltage based upon receiving the driving signal. The charge pump includes n series-connected voltage step-up stages including a first step-up stage receiving the power supply voltage and a last step-up stage producing the high voltage, at least one replacement step-up stage, and a switching circuit. The switching circuit replaces a damaged one of the n series-connected voltage step-up stages with the at least one replacement stage when a warning signal is received. A voltage regulator produces an activation signal for activating the oscillator if the high voltage is below a desired value. A detector produces the warning signal if the charge pump is defective.

公开(公告)号：FR2809246B1

公开(公告)日：2003-08-15

申请号：FR0006262

申请日：2000-05-17

Applicant: ST MICROELECTRONICS SA

Inventor： LA ROSA FRANCESCO ,  TAILLIET FRANCOIS

IPC: H03K4/50 ,  H03K17/16 ,  G11C16/14

公开(公告)号：DE69800343D1

公开(公告)日：2000-11-16

申请号：DE69800343

申请日：1998-06-09

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: G06F12/14 ,  G06F21/24 ,  G07F7/10 ,  G07F7/12 ,  G06K19/073

公开(公告)号：DE69601976T2

公开(公告)日：1999-09-09

申请号：DE69601976

申请日：1996-05-29

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: G11C16/12 ,  H03K4/02 ,  G11C16/06

Abstract: The generator includes a sampling circuit (S20,S22) which receives an input voltage and generates a sampled voltage. The sampled voltage and the generator output are added to produce a new voltage which is greater than the input voltage. A transmission or voltage follower circuit receives the new voltage and the real generator output to obtain a new generator output. The voltage follower circuit includes a first switch with an input terminal coupled to the voltage follower output terminal and a base terminal of the switch. A first capacitor is coupled to the base terminal and a reference voltage. A second switch has a first terminal coupled to a voltage follower circuit input and a third common terminal coupled to a first plate of a second capacitor. A third switch has a first terminal coupled the a reference voltage and a second terminal coupled to the base terminal. A common terminal is linked to the second plate of the second capacitor. The third capacitor is coupled to the second switch second terminal and the reference voltage.