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    31.
    发明专利
    未知

    公开(公告)号：FR2887075B1

    公开(公告)日：2007-10-12

    申请号：FR0505880

    申请日：2005-06-09

    Applicant: ST MICROELECTRONICS CROLLES 2 ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： BUSTOS JESSY ,  THONY PHILIPPE ,  CORONEL PHILIPPE

    IPC: H01L21/768 ,  H01L21/8244 ,  H01L27/11

    Abstract: A radiation attenuating layer (2) is formed above lower circuit element that is reflective to radiation. A layer transparent to radiation is formed above attenuating layer. A lithography resist mask deposited on circuit is exposed to primary radiation flux. The mask is developed to remove portions exposed to amount of radiation above mask development threshold. An upper circuit element that has one side defined by edge of attenuating layer and other side superimposed with a side of lower element is formed. An independent claim is included for integrated electronic circuit.

    DISPOSITIF A MOSFET SUR SOI
    37.
    发明专利
    DISPOSITIF A MOSFET SUR SOI 未知

    公开(公告)号：FR2911721A1

    公开(公告)日：2008-07-25

    申请号：FR0752776

    申请日：2007-01-19

    Applicant: ST MICROELECTRONICS CROLLES 2

    Inventor： CORONEL PHILIPPE ,  FENOUILLET BERANGER CLAIRE

    IPC: H01L21/84 ,  H01L27/12

    Abstract: L'invention concerne un dispositif (1) à MOSFET (106, 134) sur SOI, comprenant :- une région supérieure (102) comportant au moins un premier dispositif semi-conducteur (106) de type MOSFET disposé sur une première couche de semi-conducteur (118) empilée sur une première couche isolante (126), une première portion (128a) d'une première couche métallique et une première portion (132a) d'une seconde couche de semi-conducteur ;- une région inférieure (104) comportant au moins un second dispositif semi-conducteur (134) de type MOSFET disposé sur une seconde portion (132b) de la seconde couche de semi-conducteur, une grille (128b) du second dispositif semi-conducteur (134) étant formée par une seconde portion (128b) de la première couche métallique.La seconde couche de semi-conducteur (132) est disposée sur une seconde couche isolante (146) empilée sur une seconde couche métallique (148).

    39.
    发明专利
    未知

    公开(公告)号：FR2885733B1

    公开(公告)日：2008-03-07

    申请号：FR0504891

    申请日：2005-05-16

    Applicant: ST MICROELECTRONICS CROLLES 2

    Inventor： CORONEL PHILIPPE ,  WACQUEZ ROMAIN

    IPC: H01L29/423 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

    Abstract: Structure has a semiconductor unit (1) extending along a longitudinal direction (L1) between source and drain regions (2, 3), and comprising parts (11, 12). The part (12) is connected to a side of the part (11) on a length between the regions. A gate portion (4) is located on another side of the part (11) opposite to the part (12). Two gate portions (5, 6) are located respectively on the opposite sides of the part (12), along a direction (L2) perpendicular to the direction (L1). Electric insulation layers are located respectively between the unit and the gate portions (4, 5, 6). An independent claim is also included for: a method of forming a transistor structure.

    40.
    发明专利
    未知

    公开(公告)号：FR2894069B1

    公开(公告)日：2008-02-22

    申请号：FR0553615

    申请日：2005-11-28

    Applicant: ST MICROELECTRONICS CROLLES 2 ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： CORONEL PHILIPPE ,  GALLON CLAIRE ,  FENOUILLET BERANGER CLAIRE

    IPC: H01L21/336 ,  H01L27/11 ,  H01L29/78

    Abstract: A metal oxide semiconductor (MOS) transistor is manufactured by forming vias (50, 51, 52) contacting a gate and source and drain regions (39, 41) on other side of a channel region (30) with respect to the gate. The semiconductor layer is made of silicon and has a thickness of 5-15 nm, the dopant for forming the amorphous regions being germanium implanted at a dose of 1 x10 1>5>at/cm 2>at 3-8 keV. Manufacture of a MOS transistor comprises forming an insulated gate on a portion of a semiconductor layer of a first conductivity type delimited by a periphery, forming amorphous regions on either side of a central region of the layer underlying the gate, turning over the entire structure, totally etching the amorphous regions, where recesses are formed between the central region and the periphery, and depositing in the recesses only a conductive material capable of forming the source and drain regions of the transistor, where vias contacting the gate and the source and drain regions of the transistor are formed on the other side of a channel region with respect to the gate. The semiconductor layer is made of silicon and has a thickness of 5-15 nm, the dopant for forming the amorphous regions being germanium implanted at a dose of 1 x10 1>5>at/cm 2>at 3-8 keV.

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