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    METHOD FOR MANUFACTURING VERTICAL BIPOLAR TRANSISTOR
    31.
    发明专利
    METHOD FOR MANUFACTURING VERTICAL BIPOLAR TRANSISTOR 失效

    公开(公告)号：JP2001196385A

    公开(公告)日：2001-07-19

    申请号：JP2000353964

    申请日：2000-11-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  JOUAN SEBASTIEN ,  LLINARES PIERRE

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To propose a vertical bipolar transistor which has a reduced low-frequency noise and allowable static parameters. SOLUTION: This vertical bipolar transistor includes an intrinsic collector 4 on an extrinsic collector layer 2 buried in a semiconductor substrate, a side separation area 5 surrounding the upper part of the intrinsic collector 4, an offset extrinsic collector well 60, a base 8 which is arranged on the intrinsic collector 4 and side separation area 5 and is composed of a semiconductor area including at least one silicon layer, and two doped emitters 11 surrounded with the base 8. The emitters 11 include a first part 110 which is made of single crystal and is directly in contact with the upper surface in the predetermined window 800, and a second part 111 formed of polycrystal. These two parts are isolated by an isolated oxide layer 112 arranged at an optional distance apart from an emitter base joint part.

    EPITAXY METHOD ON SILICON SUBSTRATE INVOLVING REGIONS HEAVILY DOPED WITH BORON
    32.
    发明专利
    EPITAXY METHOD ON SILICON SUBSTRATE INVOLVING REGIONS HEAVILY DOPED WITH BORON 失效

    公开(公告)号：JP2000124132A

    公开(公告)日：2000-04-28

    申请号：JP27435199

    申请日：1999-09-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

    IPC: H01L21/302 ,  H01L21/205 ,  H01L21/22 ,  H01L21/3065 ,  H01L21/203

    Abstract: PROBLEM TO BE SOLVED: To avoid self-doping by etching a Si substrate by a specified thickness with a silicon chloride compound gas introduced before depositing in the vapor phase epitaxial deposition on the Si substrate having high-concentration dopant regions. SOLUTION: In the vapor phase epitaxial deposition on a Si substrate 1 having dopant regions 6, 7 containing boron at a high concentration, the initial annealing is selectively made and the epitaxial deposition is made for a given time to obtain an epitaxial layer 5 having a desired usual thickness. Before the epitaxial deposition, a silicon chloride compound gas is introduced to etch the Si substrate 1 by a thickness of about 100 nm or less to thereby remove a self-doped layer of boron to the epitaxial layer 5. Thus the self-doping of boron to the epitaxial layer 5 is reduced.

    Formation of single crystal semiconductor film portion separated from substrate
    33.
    发明专利
    Formation of single crystal semiconductor film portion separated from substrate 审中-公开
    形成从衬底分离的单晶半导体膜部分

    公开(公告)号：JP2007243174A

    公开(公告)日：2007-09-20

    申请号：JP2007032606

    申请日：2007-02-13

    Applicant: St Microelectronics Sa ,  エス テ マイクロエレクトロニクス エス アー

    Inventor： DUTARTRE DIDIER ,  LOUBET NICOLAS ,  TALBOT ALEXANDRE

    IPC: H01L21/762 ,  H01L21/76 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a MOS transistor comprising a single crystal semiconductor film with no facets that is formed on a void portion, a laminated structure of single crystal thin films that prevents reduction in the device surface area, and a channel region that has a homogeneous thickness and is separated from an underlying semiconductor wafer by at least one non-single crystal layer with a homogeneous thickness.
    SOLUTION: A method of forming a single crystal semiconductor film portion separated from a substrate comprises: a step of growing a single crystal semiconductor sacrifice film 38 and a single crystal semiconductor film 40 on a single crystal semiconductor active region in an insulation region 34 by selective epitaxial growth; a step of at least partially removing the raised insulation region 34; a step of removing the single crystal semiconductor sacrifice film 38 from the side, leaving a void; and a step of filling the void with an insulator, an electrical conductor, or a heat conductor.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供一种制造包括单晶半导体膜的MOS晶体管的方法，所述单晶半导体膜没有形成在空隙部分上的小面，单晶薄膜的层压结构防止器件表面积的降低 以及具有均匀厚度并且通过至少一个均匀厚度的非单晶层与下面的半导体晶片分离的沟道区域。 解决方案：形成从衬底分离的单晶半导体膜部分的方法包括：在绝缘区域的单晶半导体有源区上生长单晶半导体牺牲膜38和单晶半导体膜40的步骤 34通过选择性外延生长; 至少部分去除凸起绝缘区域34的步骤; 从侧面去除单晶半导体牺牲膜38留下空隙的步骤; 以及用绝缘体，电导体或导热体填充空隙的步骤。 版权所有（C）2007，JPO＆INPIT

    METHOD OF DEPOSITION BY EPITAXY OF SILICON LAYER ON HIGHLY DOPED SILICON SUBSTRATE
    34.
    发明专利
    METHOD OF DEPOSITION BY EPITAXY OF SILICON LAYER ON HIGHLY DOPED SILICON SUBSTRATE 失效

    公开(公告)号：JP2000040668A

    公开(公告)日：2000-02-08

    申请号：JP13872099

    申请日：1999-05-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

    IPC: H01L21/225 ,  H01L21/205 ,  H01L21/22 ,  H01L21/74 ,  H01L21/8249 ,  H01L27/06

    Abstract: PROBLEM TO BE SOLVED: To limit doping of a growth layer without increasing boron self-doping, by a method wherein an epitaxially grown silicon layer is deposited on a single crystalline silicon substrate that comprises zones of high concentrations of arsenic or phosphorus restraining it from being self-doped with arsenic or phosphorus. SOLUTION: Germanium compound as GeH4 gas is added in the gas phase during an annealing time from a point of time t5 to a point of time t6, a deposition process is stopped from a point, of time t6 to a point, of time t2, and a time t5 to t6 for adding a compound GeH4 is selectively set at ten seconds to tens of seconds. After Ge is deposited, hydrogen is purged for a time (tens of seconds) t6 to t2 at a temperature T1. An epitaxially grown silicon layer is self-doped for a time t3 to t4 and a block doped with arsenic and a non-doped block are formed at this deposition of Ge. Ge is deposited on a second test wafer of an epitaxially grown non-doped silicon layer for a time t5 to t6, and hydrogen is adsorbed and/or desorbed.

    PROCEDE DE FORMATION D'UNE PORTION MONOCRISTALLINE A BASE DE SILICIUM
    37.
    发明专利
    PROCEDE DE FORMATION D'UNE PORTION MONOCRISTALLINE A BASE DE SILICIUM 未知

    公开(公告)号：FR2900277A1

    公开(公告)日：2007-10-26

    申请号：FR0603453

    申请日：2006-04-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  RUBALDO LAURENT ,  TALBOT ALEXANDRE

    IPC: H01L21/306

    Abstract: Des portions monocristallines (2) à base de silicium sont réalisées sur une surface (S) d'un substrat (100), sélectivement dans des zones (101) où un matériau monocristallin est initialement découvert. Pour cela, une couche (1) est d'abord formée sur toute la surface du substrat, en utilisant un précurseur de silicium du type hydrure non-chloré, et dans des conditions adaptées de sorte que la couche est monocristalline dans les zones du substrat où un matériau monocristallin est initialement découvert, et amorphe en dehors de ces zones. Les portions amorphes de la couche (1) sont ensuite sélectivement gravées, de sorte que seules les portions monocristallines (2) de la couche restent sur le substrat.

    FORMATION D'UNE PORTION DE COUCHE SEMICONDUCTRICE MONOCRISTALLINE SEPAREE D'UN SUBSTRAT
    38.
    发明专利
    FORMATION D'UNE PORTION DE COUCHE SEMICONDUCTRICE MONOCRISTALLINE SEPAREE D'UN SUBSTRAT 未知

    公开(公告)号：FR2897471A1

    公开(公告)日：2007-08-17

    申请号：FR0650474

    申请日：2006-02-10

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  LOUBET NICOLAS ,  TALBOT ALEXANDRE

    IPC: H01L21/20 ,  H01L21/336

    Abstract: L'invention concerne un procédé de formation d'une portion de couche semiconductrice monocristalline (40) au dessus d'une zone évidée, comprenant les étapes consistant à faire croître par épitaxie sélective sur une région active semiconductrice monocristalline (32) une couche semiconductrice monocristalline sacrificielle (38) et une couche semiconductrice monocristalline (40), et éliminer la couche sacrificielle (38). La croissance épitaxiale est réalisée alors que la région active est entourée d'une couche isolante en surépaisseur (34) et l'élimination de la couche semiconductrice monocristalline sacrificielle (38) est effectuée par un accès résultant d'une élimination au moins partielle de la couche isolante en surépaisseur.

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