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    31.
    发明专利
    未知

    公开(公告)号：DE602006009091D1

    公开(公告)日：2009-10-22

    申请号：DE602006009091

    申请日：2006-07-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CASTALDO ENRICO ,  CONTE ANTONINO ,  LO GIUDICE GIANBATTISTA

    IPC: G11C5/14 ,  H02M3/07

    Abstract: There is disclosed an integrated control circuit (3) for a charge pump (1). The integrated circuit comprises a first device (112,N1,N2,R,12) suitable for regulating the output voltage (Vout) of the charge pump (1) and a second device (113,M10,M11,C11,11) suitable for increasing the output voltage (Vout) from the charge pump with a set ramp. The integrated circuit comprises means (111) suitable for activating said first device and providing it with a first value of a supply signal (Ireg) in a first period of time (A) and suitable for activating said second device and for providing it with a second value (Iramp) of the supply signal that is greater than the first value in a second period of time (C) after the first in such a way that the output voltage of the charge pump ascends a ramp from a first value (Vlow) to a second value (Vhigh) that is greater than the first value, said second value being fixed by the reactivation of the first device.

    33.
    发明专利
    未知

    公开(公告)号：IT1319395B1

    公开(公告)日：2003-10-10

    申请号：ITMI992149

    申请日：1999-10-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONTE ANTONINO ,  GAIBOTTI MAURIZIO ,  ZERILLI TOMMASO

    IPC: G11C7/06 ,  G11C7/14

    Abstract: A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.

    37.
    发明专利
    未知

    公开(公告)号：DE60123925D1

    公开(公告)日：2006-11-30

    申请号：DE60123925

    申请日：2001-04-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONTE ANTONINO ,  CONCEPITO ORESTE

    IPC: G05F3/22 ,  G05F3/24

    Abstract: The present invention relates to a current reference circuit for low supply voltages comprising a current source (I), connected at a side to a supply voltage (Vcc) and to the other side to a series (21) composed by a resistance (R2) and diode (D1), said diode (D1) having the cathode electrode connected to the ground and the anode electrode connected with said resistance (R2), characterized in that to comprise also a transistor (M1) and an operational amplifier (OP), said transistor (M1) having the gate electrode connected to the output of said operational amplifier (OP), said transistor (M1) having the source electrode connected to the ground, said transistor (M1) having the drain electrode connected to the positive electrode of said operational amplifier (OP), with said current source (I) and with said series (21), said operational amplifier (OP) having the negative electrode connected to a band gap reference voltage (VBG).

    39.
    发明专利
    未知

    公开(公告)号：ITVA20020020A1

    公开(公告)日：2003-09-04

    申请号：ITVA20020020

    申请日：2002-03-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CASTALDO ENRICO ,  CONTE ANTONINO

    IPC: H02M3/07

    Abstract: A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal. A phase generator circuit has an input for receiving the timing signal from the logic control circuit for generating control phases for the charge pump.

    40.
    发明专利
    未知

    公开(公告)号：ITMI20002763A1

    公开(公告)日：2002-06-20

    申请号：ITMI20002763

    申请日：2000-12-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONTE ANTONINO ,  LA ROCCA ROSANNA MARIA ,  MATRANGA GIOVANNI

    IPC: G11C16/28

    Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.

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