公开(公告)号：FR2872357A1

公开(公告)日：2005-12-30

申请号：FR0451325

申请日：2004-06-24

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE YVAN ,  TEGLIA YANNICK

IPC: H03K3/84

Abstract: L'invention concerne un procédé et un circuit de détection d'une éventuelle perte de caractère équiprobable d'un premier flux de bits de sortie (NBS1) issu d'au moins un premier élément de normalisation (3) d'un flux de bits initial (BS), consistant à soumettre le flux initial à au moins un deuxième élément de normalisation (4) de nature différente du premier, apparier (8), bit à bit, les flux issus des deux éléments, et vérifier (5, 9) l'équirépartition des paires d'états différents.

公开(公告)号：FR2841015A1

公开(公告)日：2003-12-19

申请号：FR0207488

申请日：2002-06-18

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE YVAN

IPC: G06F11/28 ,  G06F11/36 ,  G06F12/14

Abstract: Method for controlling the execution of a program implementing successive instructions each comprising at least the execution of an operator (OPEj). During the execution of each instruction: a digital signature (SIGN) is determined for each operator taking into account at least a part of an operator digital identification code and at least partially a digital code identifying the position of the operator within the program, without taking into account the values of the instruction operands; and comparison of the calculated signature with an expected value stored in memory. The invention also relates to a corresponding processor for program execution.

公开(公告)号：DE602006020010D1

公开(公告)日：2011-03-24

申请号：DE602006020010

申请日：2006-12-18

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN ,  POMET ALAIN

IPC: H04L9/06

公开(公告)号：DE602004030295D1

公开(公告)日：2011-01-13

申请号：DE602004030295

申请日：2004-02-23

Applicant: ST MICROELECTRONICS SA

Inventor： ZAHRA CLAUDE ,  TEGLIA YANNICK

IPC: G01R31/317 ,  G06F21/74 ,  G06K19/07

公开(公告)号：DE602005009439D1

公开(公告)日：2008-10-16

申请号：DE602005009439

申请日：2005-07-05

Applicant: PROTON WORLD INT NV ,  ST MICROELECTRONICS SA

Inventor： DAEMEN JOAN ,  GUILLEMIN PIERRE ,  ANGUILLE CLAUDE ,  BAEDOUILLET MICHEL ,  LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: H04L9/18 ,  G06F12/14 ,  G06F21/00

Abstract: The method involves applying a ciphering algorithm with a function of a key specific to an integrated circuit of an initialization vector. A ciphered data is memorized, where the initialization vector includes a storage address of the data in a memory and a differentiation value. An algorithm identical to the ciphering algorithm is applied based on the address of the ciphered data. An independent claim is also included for a smart card comprising an electronic assembly.

公开(公告)号：DE602004015374D1

公开(公告)日：2008-09-11

申请号：DE602004015374

申请日：2004-07-30

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN

IPC: G06F21/24 ,  G06F21/22 ,  H04L9/06 ,  H04L9/10

Abstract: The functional processes are divided into steps such that each process is interrupted with the storage of intermediary result, at the end. The steps of consecutive processes are executed successively and the process of next step is selected according to the result of random drawing of a number. An independent claim is also included for processor for executing identical functional processes.

公开(公告)号：DE602005003258D1

公开(公告)日：2007-12-27

申请号：DE602005003258

申请日：2005-04-22

Applicant: ST MICROELECTRONICS SA

Inventor： LLARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: G06F21/72 ,  G06F21/75 ,  G06F21/77

Abstract: The process involves starting an execution of a calculation, and starting another execution of the same calculation once the former execution has freed a block and its process in a second. The executions are synchronized such that the latter execution uses a hardware block only when the former execution passes to the next block. The identity between the two results is verified at the end of execution of both the calculations. An independent claim is also included for a chip card.

公开(公告)号：DE60021844T2

公开(公告)日：2006-06-01

申请号：DE60021844

申请日：2000-12-06

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F1/00 ,  G06F12/14 ,  G06F13/38 ,  G06F21/55 ,  G06F21/62 ,  H04L9/34

Abstract: The secured data transfer operates within a programmable circuit containing a processor, controller (UC), ROM and RAM, with a data bus (DBUS) connecting the memories. N octets of secret data are transferred over the data bus, and the octets are sent in a different order each time the data transfer is made, under control of a random number generator (GA).

公开(公告)号：FR2840083A1

公开(公告)日：2003-11-28

申请号：FR0206365

申请日：2002-05-24

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F7/72 ,  G06F11/36 ,  H04K1/00 ,  H04L9/06 ,  H04L9/28

公开(公告)号：FR2802668A1

公开(公告)日：2001-06-22

申请号：FR9915795

申请日：1999-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F1/00 ,  G06F7/58 ,  G06F12/14 ,  G06F13/38 ,  G06F21/55 ,  G06F21/62 ,  H04L9/10

Abstract: The secure data transfer operates in a programmable circuit containing a controller (UC), ROM and RAM, connected by a data bus (DBUS). N octets of secret data are transferred over the data bus, and the octets are sent in a different order each time the data transfer is made, using a transfer rule that has a parameter chosen at random before each transfer, using a random number generator (GA).