公开(公告)号：FR2856163A1

公开(公告)日：2004-12-17

申请号：FR0307088

申请日：2003-06-12

Applicant: ST MICROELECTRONICS SA

Inventor： BARDOUILLET MICHEL ,  ORLANDO WILLIAM ,  MALHERBE ALEXANDRE ,  ANGUILLE CLAUDE

IPC: G06F7/58

Abstract: The circuit has an input shift register (41) to receive bits flow and a comparator (42) to compare content of the register with predetermined patterns stored in a table (43). A load detector (44) detects overflow of counters with respect to a determined threshold. The detector provides the result to condition the state of a word or randomness validation bit of bit stream provided by random number generator.

公开(公告)号：AU2003226880A1

公开(公告)日：2003-09-04

申请号：AU2003226880

申请日：2003-02-11

Applicant: ST MICROELECTRONICS SA

Inventor： BARDOUILLET MICHEL ,  RIZZO PIERRE ,  MALHERBE ALEXANDRE ,  WUIDART LUC

IPC: G06F21/06 ,  G11C16/22 ,  G11C17/14 ,  H01L27/10

Abstract: The invention relates to a memory cell with a binary value consisting of two parallel branches. Each of said branches comprises: at least one polycrystalline silicon programming resistor (Rp 1 , Rp 2 ), which is connected between a first supply terminal ( 1 ) and a point or terminal for the differential reading ( 4, 6 ) of the memory cell state; and at least one first switch (MNP 1 , MNP 2 ) which, during programming, connects one of said read terminals to a second supply terminal ( 2 ).

公开(公告)号：AU2003226879A1

公开(公告)日：2003-09-04

申请号：AU2003226879

申请日：2003-02-11

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  BARDOUILLET MICHEL ,  MALHERBE ALEXANDRE

IPC: G11C16/22 ,  G11C17/14

Abstract: A one-time programmable memory cell and the programming thereof including a programming transistor which is disposed in series with a polycrystalline silicon programming resistor forming the memory element. The programming is non-destructive with respect to the polycrystalline silicon resistor.

公开(公告)号：DE602006021126D1

公开(公告)日：2011-05-19

申请号：DE602006021126

申请日：2006-12-19

Applicant: ST MICROELECTRONICS SA

Inventor： MALHERBE ALEXANDRE ,  DUVAL BENJAMIN

IPC: G06K19/073

公开(公告)号：DE602004013885D1

公开(公告)日：2008-07-03

申请号：DE602004013885

申请日：2004-06-10

Applicant: ST MICROELECTRONICS SA

Inventor： BARDOUILLET MICHEL ,  ORLANDO WILLIAM ,  MALHERBE ALEXANDRE ,  ANGUILLE CLAUDE

IPC: G06F7/58 ,  H03K3/84

Abstract: The circuit has an input shift register (41) to receive bits flow and a comparator (42) to compare content of the register with predetermined patterns stored in a table (43). A load detector (44) detects overflow of counters with respect to a determined threshold. The detector provides the result to condition the state of a word or randomness validation bit of bit stream provided by random number generator.

公开(公告)号：FR2836749A1

公开(公告)日：2003-09-05

申请号：FR0201644

申请日：2002-02-11

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  MALHERBE ALEXANDRE ,  BARDOUILLET MICHEL

IPC: G11C16/22 ,  G11C17/14 ,  G11C16/10 ,  G11C17/00

Abstract: The binary memory cell has two parallel branches. Each branch has a polycrystalline silicon programming resistor (Rp1,Rp2) connected to a terminal (1). There is a terminal point for a differential reading (4,6) of the memory state. There are switches (MNP1,MNP2) which during programming connect one of the read terminals to a second terminal (2).

公开(公告)号：FR2831328A1

公开(公告)日：2003-04-25

申请号：FR0113675

申请日：2001-10-23

Applicant: ST MICROELECTRONICS SA

Inventor： MALHERBE ALEXANDRE ,  BLISSON FABRICE

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L23/60

Abstract: The integrated circuit (20) includes a metal oxide semiconductor (MOS) transistors which are provided for short-circuiting the supply conductors (12,13) arranged in a supply rail (11). The MOS transistors are integrated in the supply rail, below the conductors. The control circuits (6) detect electrostatic discharge (ESD) and overvoltage between the supply conductors. An Independent claim is also included for method of integrating MOS transistors for short- circuiting the supply conductors.

公开(公告)号：FR2804521A1

公开(公告)日：2001-08-03

申请号：FR0001061

申请日：2000-01-27

Applicant: ST MICROELECTRONICS SA

Inventor： POMET ALAIN ,  MALHERBE ALEXANDRE ,  MARINET FABRICE

IPC: G06F13/42 ,  G06K19/07 ,  G06F1/04 ,  H04L7/00 ,  H03L7/00

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.