Abstract:
A multilevel memory device comprises an array of multilevel memory cells (M 1j - M kj , M 1z - M kz ) arranged in rows (WL 1 - WL k ) and columns (BL j , BL z ), each memory cell being capable of being programmed in m = 2 n ( n > 1) distinct programming states, and a sensing arrangement for sensing the memory cells, the sensing arrangement comprising at least ( m - 1) reference columns (BL ref,i , BL ref,h ) of memory cells. The reference columns comprises a number of memory cells substantially identical to the number of memory cells of each column of the array, a smaller number of memory cells (M ref,i , M, ref,h ) of each reference column being multilevel reference memory cells programmed in a respective reference programming state and activatable for sinking a respective reference current (I R,0 ,I R,1 ,I R,2 ), the remaining larger number of memory cells of each reference column being dummy non-conductive memory cells (M dumr,1i - M dumr,ki , M dumr,1h - M dumr,kh ) structurally identical to the reference memory cells and to the memory cells of the array.