Sensing arrangement for a multilevel semiconductor memory device
    31.
    发明公开
    Sensing arrangement for a multilevel semiconductor memory device 有权
    AusleseanordnungfürMultibit-Halbleiterspeicheranordnung

    公开(公告)号:EP0978844A1

    公开(公告)日:2000-02-09

    申请号:EP98830491.1

    申请日:1998-08-07

    CPC classification number: G11C11/5642 G11C11/5621 G11C2211/5634

    Abstract: A multilevel memory device comprises an array of multilevel memory cells (M 1j - M kj , M 1z - M kz ) arranged in rows (WL 1 - WL k ) and columns (BL j , BL z ), each memory cell being capable of being programmed in m = 2 n ( n > 1) distinct programming states, and a sensing arrangement for sensing the memory cells, the sensing arrangement comprising at least ( m - 1) reference columns (BL ref,i , BL ref,h ) of memory cells. The reference columns comprises a number of memory cells substantially identical to the number of memory cells of each column of the array, a smaller number of memory cells (M ref,i , M, ref,h ) of each reference column being multilevel reference memory cells programmed in a respective reference programming state and activatable for sinking a respective reference current (I R,0 ,I R,1 ,I R,2 ), the remaining larger number of memory cells of each reference column being dummy non-conductive memory cells (M dumr,1i - M dumr,ki , M dumr,1h - M dumr,kh ) structurally identical to the reference memory cells and to the memory cells of the array.

    Abstract translation: 多级存储器件包括以行(WL1-WLK)和列(BLj,BLz)排列的多级存储器单元阵列(M1j-Mkj,M1z-Mkz),每个存储器单元能够被编程为m = 2 1)不同的编程状态,以及用于感测存储器单元的感测装置,所述感测装置包括至少(m-1)个存储器单元的参考列(BLref,i,BLref,h)。 参考列包括与阵列的每列的存储单元的数量基本相同的多个存储器单元,每个参考列的较小数量的存储器单元(Mref,i,M,ref,h)是多电平参考存储器单元 编程在相应的参考编程状态并且可激活以吸收相应的参考电流(IR,0,IR,1,IR,2),每个参考列的剩余较大数量的存储单元是虚拟非导电存储器单元(Mdumr, 1i-Mdumr,ki,Mdumr,1h-Mdumr,kh)在结构上与参考存储器单元和阵列的存储器单元相同。

Patent Agency Ranking