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Patent Agency Ranking1.发明授权Successive approximation method for sensing multiple-level non-volatile memory cells and sensing circuit using such method 失效部一步方法方法用于非易失性多电平存储器单元和对应的采样的扫描
公开(公告)号：EP0724266B1
公开(公告)日：2001-12-12
申请号：EP95830023.8
申请日：1995-01-27
Applicant: STMicroelectronics S.r.l.
Inventor： Calligaro, Cristiano , Daniele, Vincenzo , Gastaldi, Roberto , Manstretta, Alessandro , Torelli, Guido
IPC: G11C11/56
CPC classification number: G11C11/5642 , G11C11/5621 , G11C2211/5632
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2.发明授权Sensing circuit for serial dichotomic sensing of multiple-levels non-volatile memory cells 失效阅读多层非易失性存储单元的二分串行感测电路
公开(公告)号：EP0734024B1
公开(公告)日：2000-01-26
申请号：EP95830110.3
申请日：1995-03-23
Applicant: STMicroelectronics S.r.l.
Inventor： Calligaro, Cristiano , Daniele, Vincenzo , Gastaldi, Roberto , Manstretta, Alessandro , Telecco, Nicola , Torelli, Guido
IPC: G11C11/56
CPC classification number: G11C11/5621 , G11C11/5642 , G11C2211/5632
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3.发明授权Programmable device with basic modules electrically connected by flash memory cells 失效与由快闪存储单元的装置相互连接的基本模块的可编程器件
公开(公告)号：EP0782144B1
公开(公告)日：2001-05-23
申请号：EP95830552.6
申请日：1995-12-29
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele, Vincenzo
IPC: G11C11/00 , H03K19/177 , H03K19/173
CPC classification number: H03K19/17708 , H03K19/1736
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4.发明授权Mixed parallel-dichotomic serial sensing method for sensing multiple-levels non-volatile memory cells, and sensing circuit actuating such method 失效使用这样的方法并行非易失多电平存储器单元和感测电路的混合串行二分感测方法
公开(公告)号：EP0757355B1
公开(公告)日：2000-04-19
申请号：EP95830347.1
申请日：1995-07-31
Applicant: STMicroelectronics S.r.l.
Inventor： Calligaro, Cristiano , Daniele, Vincenzo , Gastaldi, Roberto , Manstretta, Alessandro , Telecco, Nicola , Torelli, Guido
IPC: G11C11/56
CPC classification number: G11C11/5642 , G11C11/5621 , G11C2211/5632 , G11C2211/5633
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5.发明公开
公开(公告)号：EP0862270A1
公开(公告)日：1998-09-02
申请号：EP97830084.6
申请日：1997-02-28
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele, Vincenzo , Manstretta, Alessandro , Rolandi, Paolo , Torelli, Guido
Abstract: A stair-case adaptive voltage generator circuit, which circuit comprises a first capacitor (CB) connected between a first voltage reference (Vref) and an output operational amplifier (CA), through first (T1 and second (T4) switches, respectively.
The terminals of the capacitor are also connected to a second voltage reference (Vinit) through third (T3) and fourth (T2) switches, respectively.
A second capacitor (CA), in series with a fifth switch (CNT), is connected in parallel to the first capacitor (CB).Abstract translation: 一个阶梯式自适应电压发生器电路，该电路包括分别通过第一（T1和第二（T4）开关连接在第一电压基准（Vref）和输出运算放大器（CA）之间的第一电容器（CB）。 电容器的端子也分别通过第三（T3）和第四（T2）开关连接到第二参考电压（Vinit），与第五开关（CNT）串联的第二电容器（CA）并联 到第一个电容（CB）
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