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    Non-volatile memory device with configurable row redundancy
    8.
    发明公开
    Non-volatile memory device with configurable row redundancy 有权
    NichtflüchtigeSpeicheranordnung mit konfigurierbarer Zeilenredundanz

    公开(公告)号：EP1126372A1

    公开(公告)日：2001-08-22

    申请号：EP00830103.8

    申请日：2000-02-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Manstretta, Alessandro ,  Micheloni, Rino ,  Pierin, Andrea ,  Yero, Emilio

    IPC: G06F11/20

    CPC classification number: G11C29/70

    Abstract: This invention relates to a non-volatile memory device (20) with configurable row redundancy, comprising:

    a non-volatile memory (11) comprising of at least one matrix (11') of memory cells and at least one matrix (11") of redundant memory cells, both organised into rows and columns;
    row and column decoding circuits (12,13);
    read and modify circuits for reading and modifying data stored in the memory cells; and
    at least one associative memory matrix (14), also organised into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix.

    The memory device (20) of this invention further comprises:

    at least one circuit for recognising and comparing selected row addresses (ADr) with faulty row addresses (ADrr) contained in the associative memory matrix (14), such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and
    at least one configuration register (17), also comprising a matrix of non-volatile memory cells, and associated control circuits.

    Abstract translation: 本发明涉及一种具有可配置行冗余性的非易失性存储器件（20），包括：非易失性存储器（11），包括至少一个存储器单元矩阵（11'）和至少一个矩阵（11“）， 冗余存储器单元，被组织成行和列;行和列解码电路（12,13）;用于读取和修改存储在存储器单元中的数据的读取和修改电路;以及至少一个关联存储器矩阵（14） 本发明的存储器件（20）还包括：用于识别和比较所选行地址（ADr）的至少一个电路 ），包括在所述关联存储器矩阵（14）中的有缺陷的行地址（ADrr），以便在有效识别的情况下产生故障行的选择和对应的冗余单元行的选择;以及至少一个配置 （17），还包括非易失性存储器单元矩阵和相关联的控制电路。

    Method for programming multi-level non-volatile memories by controlling the gate voltage
    9.
    发明公开
    Method for programming multi-level non-volatile memories by controlling the gate voltage 有权
    Programmierungverfahren einesnichtflüchtigenMultibit Speichers durch Regelung der Gatespannung

    公开(公告)号：EP1074995A1

    公开(公告)日：2001-02-07

    申请号：EP99830501.5

    申请日：1999-08-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Torelli, Guido ,  Modelli, Alberto ,  Manstretta, Alessandro

    IPC: G11C11/56

    CPC classification number: G11C11/5621 ,  G11C11/5628

    Abstract: When programming, for each programming pulse, a threshold voltage whose value is increased with respect to the previous programming pulse is applied to the gate terminal of each cell to be programmed. After an initial step, the increase of threshold voltage of the cell being programmed becomes equal to the applied gate voltage increase (ΔV GP ). In order to reduce the global programming time, keeping a small variability interval of threshold voltages associated with each level, to pass from a threshold level to a following one, each cell to be programmed is supplied with a plurality of consecutive pulses without verify (107-109), until it immediately goes below the voltage level to be programmed, and then a verify step (110) is performed, followed by subsequent programming and verify steps (112, 110, 117, 118) until the cell to be programmed reaches the desired threshold value.

    Abstract translation: 当编程时，对于每个编程脉冲，其值相对于先前编程脉冲增加的阈值电压被施加到要编程的每个单元的栅极端子。 在初始步骤之后，被编程的单元的阈值电压的增加等于施加的栅极电压增加（DELTA VGP）。 为了减少全局编程时间，保持与每个电平相关联的阈值电压的小变化间隔从阈值电平传递到随后的每个要编程的每个单元被提供多个连续的脉冲而不验证（107 -109），直到其立即低于要编程的电压电平，然后执行验证步骤（110），随后进行后续编程和验证步骤（112,110,117,118），直到待编程的单元达到 所需的阈值。

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