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    Improved field-effect transistor and corresponding manufacturing method
    31.
    发明公开
    Improved field-effect transistor and corresponding manufacturing method 审中-公开
    Verbesserter Feldeffekttransistor和Verfahren zu dessen Herstellung

    公开(公告)号：EP1003222A1

    公开(公告)日：2000-05-24

    申请号：EP98830694.0

    申请日：1998-11-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico ,  Zuliani, Paola

    IPC: H01L29/10 ,  H01L21/336 ,  H01L21/266

    CPC classification number: H01L29/1041 ,  H01L21/76202

    Abstract: Field effect transistor (1) integrated on a semiconductor substrate (4) with a respective active area (8) comprising:

    a region of source (2) and a region of drain (3) formed in the semiconductor substrate (4),
    a channel region (5) interposed between said regions of source (2) and of drain (3) having a predefined nominal width (W N ), wherein said channel region (5) has an effective width (Weff) defined by a variable profile of doping.

    Abstract translation: 集成在具有相应有源区域（8）的半导体衬底（4）上的场效应晶体管（1）包括：源极（2）的区域和形成在半导体衬底（4）中的漏极（3）的区域，沟道 位于源极（2）的所述区域和具有预定标称宽度（WN）的漏极（3）的所述区域之间的区域（5），其中所述沟道区域（5）具有由掺杂的可变轮廓限定的有效宽度（Weff）。

    Circuit structure comprising a parasitic transistor having a very high threshold voltage
    32.
    发明公开
    Circuit structure comprising a parasitic transistor having a very high threshold voltage 失效
    Schaltkreis mit einemparasitären晶体管hoher Einsatzspannung

    公开(公告)号：EP0977265A1

    公开(公告)日：2000-02-02

    申请号：EP98830461.4

    申请日：1998-07-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Dalla Libera, Giovanna ,  Pio, Federico

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/49

    CPC classification number: H01L27/088 ,  H01L21/823475

    Abstract: A circuit structure integrated in a semiconductor substrate (40) comprises at least one pair of transistors (20,21) being formed each in a respective active area region (30) and having a source region (22) and a drain region (23), as well as a channel region (24) intervening between the source and drain regions (22,23) and being overlaid by a gate region (25); the gate regions (25) are connected electrically together by an overlying conductive layer (28) and respective contacts (14) wherein the contacts (14) between the gate regions (24) and the conductive layer (28) are formed above the active areas (30).

    Abstract translation: 集成在半导体衬底（40）中的电路结构包括至少一对晶体管（20,21），每个晶体管分别形成在相应的有源区域（30）中并且具有源极区（22）和漏极区（23） ，以及介于源区和漏区（22,23）之间并被栅极区域（25）覆盖的沟道区（24）; 栅极区域（25）通过覆盖的导电层（28）和相应的触点（14）电连接在一起，其中栅极区域（24）和导电层（28）之间的触点（14）形成在有源区域 （30）。

    An electronic structure comprising high and low voltage transistors, and a corresponding manufacturing method
    33.
    发明公开
    An electronic structure comprising high and low voltage transistors, and a corresponding manufacturing method 审中-公开
    电子组件具有高电压和低电压晶体管和它们的制备方法

    公开(公告)号：EP0954029A1

    公开(公告)日：1999-11-03

    申请号：EP98204129.5

    申请日：1998-12-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico ,  Pizzuto, Olivier

    IPC: H01L27/105 ,  H01L21/8239 ,  H01L21/8234

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    Abstract: A structure of electronic devices integrated in a semiconductor substrate with a first type of conductivity comprising at least a first HV transistor and at least a second LV transistor, each having a corresponding gate region. Said first HV transistor has lightly doped drain and source regions with a second type of conductivity, and said second LV transistor has respective drain and source regions with the second type of conductivity, each including a lightly doped portion adjacent to the respective gate region and a second portion which is more heavily doped and comprises a silicide layer.

    Abstract translation: 集成在一个半导体衬底具有第一导电类型的至少一个包括第一晶体管HV和至少一个第二LV晶体管，各具有一个栅极对应区域的电子设备的结构。 所述第一HV晶体管具有轻掺杂漏极和源极区具有第二导电类型，和所述第二LV晶体管具有与所述第二导电类型的respectivement漏极和源极区域，每个区域包括一个轻掺杂部分毗邻respectivement栅极区和一个 第二部分全部被更重掺杂，并且包括硅化物层。

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    34.
    发明公开
    "Non-volatile memory cell and corresponding manufacturing process". 失效
    Festwertspeicherzelle und deren Herstellungsverfahren

    公开(公告)号：EP0930655A1

    公开(公告)日：1999-07-21

    申请号：EP98201715.4

    申请日：1998-05-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pio, Federico

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    Abstract: The invention relates to a non-volatile memory cell and a manufacturing process therefor.
    The cell (1,10) is integrated in a semiconductor substrate (2) and comprises:

    a floating gate transistor (3,30) having a first source region (17,170), first drain region (15,150), and gate region (5,50) projecting over the substrate (2) and intervening between the first source and drain regions (17,15;170,150); and
    a selection transistor (4,40) having a second source region (19,190), second drain region (20,200), and respective gate region (23,230), projecting over the substrate (2), between the second source and drain regions (19,20;190,200). The first and second regions are lightly doped and the cell comprises mask elements (31a, 310a).

    Abstract translation: 本发明涉及一种非易失性存储单元及其制造方法。 电池（1,10）集成在半导体衬底（2）中，包括：具有第一源极区（17,170），第一漏极区（15,150）和栅极区（5）的浮栅晶体管（3,30） 50）突出在所述基板（2）上并且介于所述第一源极和漏极区域（17,15; 170,150）之间; 以及在所述第二源极和漏极区域（19）之间具有突出于所述衬底（2）上的第二源极区域（19,190），第二漏极区域（20,200）和相应栅极区域（23,230）的选择晶体管（4,40） ，20; 190200）。 第一和第二区域被轻掺杂，并且电池包括掩模元件（31a，310a）。

    Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations
    39.
    发明公开
    Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations 有权
    一种用于阈值电压的变细处理在写入操作期间被擦除闪存单元

    公开(公告)号：EP1909290A1

    公开(公告)日：2008-04-09

    申请号：EP06119452.8

    申请日：2006-08-24

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Micheloni, Rino ,  Crippa, Luca ,  Ravasio, Roberto ,  Pio, Federico

    IPC: G11C16/34

    CPC classification number: G11C16/344

    Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

    Abstract translation: 一种用于操作闪存器件（100）的方法，提出了 所述存储器装置包含存储单元的矩阵（110）每一个具有 - 定义存储在存储单元中的值的可编程阈值电压（V T）。 该方法包括crasing存储器单元的块（115），以及预定义的压实范围内压实块的存储器单元的阈值电压，worin压实的步骤的步骤包括：选择至少一个第一存储单元（110 0E）用于写入目标值的块的; 的子集的阈值电压（110 0E; 110 1O）恢复该块的存储器单元内的压实范围，所述子集由......组成所述至少一个第一存储单元（110奥斯特）和/或至少一个第二存储单元 块（110 1O）邻近所述至少一个第一存储单元的; 并至少部分地写入目标值到所述至少一个第一存储单元。

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