公开(公告)号：US20230187598A1

公开(公告)日：2023-06-15

申请号：US17583222

申请日：2022-01-25

Applicant: Unimicron Technology Corp.

Inventor： Wen-Yu Lin ,  Kai-Ming Yang

IPC: H01L33/64 ,  H01L25/075 ,  H01L33/22 ,  H01L33/48 ,  H01L33/62

CPC classification number: H01L33/647 ,  H01L25/0753 ,  H01L33/22 ,  H01L33/483 ,  H01L33/62 ,  H01L2933/0066 ,  H01L2933/0075

Abstract: A light-emitting diode package structure includes a heat dissipation substrate, a redistribution layer, and multiple light-emitting diodes. The heat dissipation substrate includes multiple copper blocks and a heat-conducting material layer. The copper blocks penetrate the heat-conducting material layer. The redistribution layer is disposed on the heat dissipation substrate and electrically connected to the copper blocks. The light-emitting diodes are disposed. on the redistribution layer and are electrically connected to the redistribution layer. A side of the light-emitting diodes away from the redistribution layer is not in contact with any component.

公开(公告)号：US20230178520A1

公开(公告)日：2023-06-08

申请号：US17571543

申请日：2022-01-10

Applicant: Unimicron Technology Corp.

Inventor： Wen-Yu Lin ,  Kai-Ming Yang ,  Chen-Hao Lin

IPC: H01L25/075 ,  H01L33/00 ,  H01L23/00

CPC classification number: H01L25/0753 ,  H01L33/0093 ,  H01L24/19 ,  H01L24/94 ,  H01L24/20 ,  H01L33/62

Abstract: A light-emitting diode package includes a redistribution layer, a light-emitting diode, a first dielectric layer, a plurality of wavelength conversion structures, and a transparent encapsulant. The light-emitting diode is disposed on and electrically connected to the redistribution layer. The light-emitting diode includes a first light-emitting diode, a second light-emitting diode, and a third light-emitting diode. The first dielectric layer is disposed on the redistribution layer and covers the light-emitting diode. The wavelength conversion structures are disposed on the first dielectric layer and respectively in contact with the second light-emitting diode and the third light-emitting diode. The transparent encapsulant is disposed on the first dielectric layer and covers the plurality of wavelength conversion structures. In addition, a manufacturing method of the light-emitting diode package is provided.

公开(公告)号：US20220336333A1

公开(公告)日：2022-10-20

申请号：US17233551

申请日：2021-04-19

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Chi-Hai Kuo ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.

公开(公告)号：US20220246810A1

公开(公告)日：2022-08-04

申请号：US17209110

申请日：2021-03-22

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang

IPC: H01L33/62 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L33/54

Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.

公开(公告)号：US20220208630A1

公开(公告)日：2022-06-30

申请号：US17155094

申请日：2021-01-22

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Pei-Chi Chen ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78

Abstract: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.

公开(公告)号：US11219130B2

公开(公告)日：2022-01-04

申请号：US16528560

申请日：2019-07-31

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin

IPC: H05K1/11 ,  H05K3/10 ,  H05K3/18 ,  H05K3/24

Abstract: A circuit board including a substrate, a patterned conductive layer, a patterned insulating layer, a conductive terminal, and a dummy terminal is provided. The patterned conductive layer is disposed on the substrate. The patterned insulating layer is disposed on the substrate and at least covers a portion of the patterned conductive layer. The conductive terminal is disposed on the patterned conductive layer and has a first top surface. The dummy terminal is disposed on the patterned conductive layer and has a second top surface. A first height between the first top surface and the substrate is greater than a second height between the second top surface and the substrate.

公开(公告)号：US11013103B2

公开(公告)日：2021-05-18

申请号：US16203636

申请日：2018-11-29

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  Kai-Ming Yang ,  Chien-Tsai Li

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46

Abstract: A method for forming a circuit board includes forming a first dielectric layer, a first circuit layer in the first dielectric layer, a second circuit layer on the first dielectric layer, and a plurality of conductive vias in the first dielectric layer and connecting the first circuit layer to the second circuit layer; forming a second dielectric layer on the first dielectric layer and the second circuit layer; forming a plurality of openings in the second dielectric layer to expose a plurality of parts of the second circuit layer; forming a seed layer on the exposed parts of the second circuit layer and sidewalls of the openings; and forming a plurality of bonding layers on the seed layer, wherein the bonding layers and the seed layer are made of copper, and the bonding layers are porous.

公开(公告)号：US10993332B2

公开(公告)日：2021-04-27

申请号：US16746968

申请日：2020-01-20

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin

IPC: H01L29/40 ,  H05K3/46 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H05K3/32 ,  H05K3/40 ,  H01L23/488

Abstract: A circuit substrate includes a substrate, a wire build-up layer structure, and an insulating layer. The substrate has a first surface and a second surface opposites to the first surface. The substrate includes a plurality of patterned pads. The patterned pads are disposed on the first surface of the substrate, and having contact openings. The wire build-up layer structure is disposed on the first surface of the substrate. The wire build-up layer structure includes an interconnect build-up layer and a plurality of conductive pillars. The conductive pillars electrically connect to the interconnect build-up layer and the patterned pads. The insulating layer is disposed between the substrate and the wire build-up layer structure.

公开(公告)号：US20200154578A1

公开(公告)日：2020-05-14

申请号：US16746968

申请日：2020-01-20

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin

IPC: H05K3/46 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/488 ,  H05K3/32 ,  H05K3/40

Abstract: A circuit substrate includes a substrate, a wire build-up layer structure, and an insulating layer. The substrate has a first surface and a second surface opposites to the first surface. The substrate includes a plurality of patterned pads. The patterned pads are disposed on the first surface of the substrate, and having contact openings. The wire build-up layer structure is disposed on the first surface of the substrate. The wire build-up layer structure includes an interconnect build-up layer and a plurality of conductive pillars. The conductive pillars electrically connect to the interconnect build-up layer and the patterned pads. The insulating layer is disposed between the substrate and the wire build-up layer structure.

公开(公告)号：US10588214B2

公开(公告)日：2020-03-10

申请号：US16543609

申请日：2019-08-18

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Yu-Hua Chen

IPC: H05K1/02 ,  H05K1/11

Abstract: A stacked structure includes a circuit board, an electronic component, metallic cores, and insulating cladding layers. The circuit board includes first bonding pads. The electronic component includes second bonding pads that are opposite to the first bonding pads. Each metallic core is connected to a corresponding first bonding pad and a corresponding second bonding pad. The metallic cores have a curved surface interposed between the corresponding first bonding pad and the corresponding second bonding pad. The insulating cladding layers are separated from each other and cover the curved surfaces of the metallic cores.