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    Chip package structure
    31.
    发明授权
    Chip package structure 有权

    公开(公告)号：US10211139B2

    公开(公告)日：2019-02-19

    申请号：US15287729

    申请日：2016-10-06

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  Yu-Hua Chen ,  Ra-Min Tain

    IPC: H01L23/498 ,  H01L23/48 ,  H01L25/10 ,  H01L21/48 ,  H01L23/367 ,  H01L23/31 ,  C25D5/02 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  H05K1/11 ,  H05K3/46 ,  H01L23/36 ,  H05K3/42

    Abstract: A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate.

    MANUFACTURING METHOD OF INTERPOSED SUBSTRATE
    32.
    发明申请
    MANUFACTURING METHOD OF INTERPOSED SUBSTRATE 审中-公开
    嵌入式基板的制造方法

    公开(公告)号：US20160133483A1

    公开(公告)日：2016-05-12

    申请号：US14995207

    申请日：2016-01-14

    Applicant: Unimicron Technology Corp.

    Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

    IPC: H01L21/48 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  C25D5/02

    CPC classification number: H01L21/4857 ,  C25D1/003 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  H05K1/113 ,  H05K3/10 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/49155

    Abstract: A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

    Abstract translation: 提供了一种插入式基板的制造方法。 形成包括第一金属层，蚀刻停止层和第二金属层的金属层叠层。 图案化的导体层形成在第一金属层上，其中图案化的导体层露出第一金属层的一部分。 在图案化的导体层上形成多个导电柱，其中导电柱彼此分离并堆叠在图案化的导体层的一部分上。 在金属堆叠层上形成绝缘材料层，其中绝缘材料层覆盖第一金属层的部分并且封装导电柱和图案化导体层的另一部分。 去除金属层叠层以露出与绝缘材料层的上表面相反的下表面和图案化导体层的底表面。

    MANUFACTURING METHOD OF INTERPOSED SUBSTRATE
    34.
    发明申请
    MANUFACTURING METHOD OF INTERPOSED SUBSTRATE 审中-公开
    嵌入式基板的制造方法

    公开(公告)号：US20150097318A1

    公开(公告)日：2015-04-09

    申请号：US14568084

    申请日：2014-12-11

    Applicant: Unimicron Technology Corp.

    Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

    IPC: H01L21/48

    CPC classification number: H01L21/481 ,  C25D1/003 ,  H05K1/113 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T156/10

    Abstract: A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal cattier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads.An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.

    Abstract translation: 提供了一种插入式基板的制造方法。 在金属载体上形成光致抗蚀剂层。 光致抗蚀剂层具有暴露金属载体的一部分的多个开口。 多个金属钝化垫和多个导电柱形成在开口中。 金属钝化垫覆盖由开口暴露的金属载体的一部分。 导电柱分别堆叠在金属钝化垫上。 去除光致抗蚀剂层以暴露金属载体的另一部分。 在金属罐上形成绝缘材料层。 绝缘材料层覆盖金属载体的另一部分并封装导电柱和金属钝化垫。 绝缘材料层的上表面和每个导电柱的顶表面是共面的。 去除金属载体以暴露绝缘材料层的下表面。

    PACKAGE STRUCTURE
    35.
    发明申请
    PACKAGE STRUCTURE 有权

    公开(公告)号：US20250149503A1

    公开(公告)日：2025-05-08

    申请号：US18590958

    申请日：2024-02-29

    Applicant: Unimicron Technology Corp.

    Inventor： John Hon-Shing Lau ,  Tzyy-Jang Tseng

    IPC: H01L25/065 ,  G02B6/42 ,  H01L23/00 ,  H01L23/498

    Abstract: A package structure includes a package substrate, a system on a chip (SoC), at least one input/output circuit, multiple optoelectronic assemblies and an organic interposer. The SoC is disposed on the package substrate and includes a central processing unit (CPU), a graphics processing unit (GPU) and a memory. The input/output circuit is disposed on the package substrate. The optoelectronic assemblies are separately disposed on the package substrate and surround the SoC and the input/output circuit. The organic interposer is disposed on the package substrate. The SoC, the input/output circuit and the optoelectronic assemblies are electrically connected to the package substrate through the organic interposers.

    Probe card testing device
    37.
    发明授权
    Probe card testing device 有权

    公开(公告)号：US11808787B2

    公开(公告)日：2023-11-07

    申请号：US17342550

    申请日：2021-06-09

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  John Hon-Shing Lau ,  Kuo Ching Tien ,  Ra-Min Tain

    IPC: H05K1/02 ,  H05K1/03 ,  G01R1/06 ,  G01R1/07 ,  G01R1/073 ,  H05K1/11

    CPC classification number: G01R1/07342 ,  G01R1/07328 ,  H05K1/112

    Abstract: A probe card testing device includes a first sub-circuit board, a second sub-circuit board, a connecting structure layer, a fixing plate, a probe head and a plurality of conductive probes. The first sub-circuit board is electrically connected to the second sub-circuit board by the connecting structure layer. The fixing plate is disposed on the second sub-circuit board and includes an opening and an accommodating groove. The opening penetrates the fixing plate and exposes a plurality of pads on the second sub-circuit board. The accommodating groove is located on a side of the fixing plate relatively far away from the second sub-circuit board and communicates with the opening. The probe head is disposed in the accommodating groove of the fixing plate. The conductive probes are set on the probe head and in the opening of the fixing plate. One end of the conductive probes is in contact with the corresponding pads, respectively.

    CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF
    39.
    发明公开
    CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230240023A1

    公开(公告)日：2023-07-27

    申请号：US17684421

    申请日：2022-03-02

    Applicant: Unimicron Technology Corp.

    Inventor： Wen-Yu Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Chin-Sheng Wang ,  Guang-Hwa Ma ,  Tzyy-Jang Tseng

    IPC: H05K3/46 ,  H05K1/11

    CPC classification number: H05K3/467 ,  H05K1/112 ,  H05K2201/0191

    Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

    CIRCUIT BOARD STRUCTURE
    40.
    发明申请
    CIRCUIT BOARD STRUCTURE 有权

    公开(公告)号：US20220408554A1

    公开(公告)日：2022-12-22

    申请号：US17674837

    申请日：2022-02-18

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  Chin-Sheng Wang ,  Ra-Min Tain

    IPC: H05K1/02 ,  H05K1/18

    Abstract: A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, and at least one second build-up circuit layer. The dielectric substrate includes a through cavity penetrating the dielectric substrate. The embedded block is fixed in the through cavity. The embedded block includes a first through hole and a second through hole. The electronic component is disposed in the through hole of the embedded block. The first build-up circuit layer is disposed on the top surface of the dielectric substrate and covers the embedded block. The second build-up circuit layer is disposed on the bottom surface of the dielectric substrate and covers the embedded block.

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