公开(公告)号：US20180277388A1

公开(公告)日：2018-09-27

申请号：US15992223

申请日：2018-05-30

Applicant: Toshiba Memory Corporation

Inventor： Yukiteru MATSUI ,  Kyoichi SUGURO ,  Akifumi GAWASE ,  Takahiko KAWASAKI

IPC: H01L21/3115 ,  H01L21/3215 ,  H01L21/3105 ,  H01J37/317 ,  H01L21/321 ,  H01L21/306 ,  H01L21/304

CPC classification number: H01L21/31155 ,  B81C2201/0123 ,  B81C2201/0125 ,  H01J37/3171 ,  H01J2237/31711 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/3215

Abstract: A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a CMP method.

公开(公告)号：US10008390B2

公开(公告)日：2018-06-26

申请号：US14643218

申请日：2015-03-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yukiteru Matsui ,  Kyoichi Suguro ,  Akifumi Gawase ,  Takahiko Kawasaki

IPC: H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  H01L21/3115 ,  H01L21/321 ,  H01J37/317 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/3215

CPC classification number: H01L21/31155 ,  B81C2201/0123 ,  B81C2201/0125 ,  H01J37/3171 ,  H01J2237/31711 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/3215

Abstract: A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a CMP method.

公开(公告)号：US09416298B2

公开(公告)日：2016-08-16

申请号：US14402975

申请日：2013-05-21

Applicant: BASF SE

Inventor： Yuzhuo Li ,  Bastian Marten Noller ,  Christophe Gillot ,  Diana Franz

IPC: C09G1/02 ,  H01L21/304 ,  H01L21/302 ,  H01L21/321 ,  H01L21/461 ,  H01L21/306 ,  H01L21/02

CPC classification number: C09G1/02 ,  B81C2201/0121 ,  B81C2201/0123 ,  B81C2201/0126 ,  H01L21/02024 ,  H01L21/302 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/461

Abstract: A process for the manufacture of semiconductor devices comprising the chemical-mechanical polishing of a substrate or layer containing at least one III-V material in the presence of a chemical-mechanical polishing composition (Q1) comprising (A) inorganic particles, organic particles, or a mixture or composite thereof, (B) at least one amphiphilic non-ionic surfactant having (b1) at least one hydrophobic group; and (b2) at least one hydrophilic group selected from the group consisting of polyoxyalkylene groups comprising (b22) oxyalkylene monomer units other than oxyethylene monomer units; and (M) an aqueous medium.

Abstract translation: 一种用于制造半导体器件的方法，包括在化学机械抛光组合物（Q1）的存在下对包含至少一种III-V材料的基底或层进行化学机械抛光，所述化学机械抛光组合物包含（A）无机颗粒，有机颗粒， 或其混合物或复合物，（B）至少一种具有（b1）至少一个疏水基团的两亲性非离子表面活性剂; 和（b2）至少一种选自包含（b22）氧化烯单体单元以外的氧化烯单体单元的聚氧化烯基的亲水基团; 和（M）水性介质。

公开(公告)号：US20150140717A1

公开(公告)日：2015-05-21

申请号：US14543116

申请日：2014-11-17

Applicant: Robert Bosch GmbH

Inventor： Andrea URBAN

IPC: B81C1/00 ,  B81C99/00

CPC classification number: B81C1/00857 ,  B81C1/00388 ,  B81C1/00531 ,  B81C1/00849 ,  B81C99/0025 ,  B81C2201/0123 ,  B81C2201/0125 ,  B81C2201/0132

Abstract: A method is described for manufacturing a micromechanical structure, in which a structured surface is created in a substrate by an etching method in a first method step, and residues are at least partially removed from the structured surface in a second method step. In the second method step, an ambient pressure for the substrate which is lower than 60 Pa is set and a substrate temperature which is higher than 150° C. is set.

Abstract translation: 描述了一种用于制造微机械结构的方法，其中通过第一方法步骤中的蚀刻方法在衬底中形成结构化表面，并且在第二方法步骤中至少部分地从结构化表面除去残余物。 在第二方法步骤中，设定低于60Pa的基板的环境压力，设定高于150℃的基板温度。

公开(公告)号：US07781311B2

公开(公告)日：2010-08-24

申请号：US11642904

申请日：2006-12-20

Applicant: Mark Andrew Franklin ,  Georgina Marie Jabbour ,  James Carl Baker

Inventor： Mark Andrew Franklin ,  Georgina Marie Jabbour ,  James Carl Baker

IPC: H01L21/44

CPC classification number: B81C1/00611 ,  B81B2203/0353 ,  B81B2207/07 ,  B81C2201/0123 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: System and method for filling vias in integrated circuits A preferred embodiment comprises forming a spacer layer on a substrate, forming a via with walls and a bottom in the spacer layer, depositing a conformal conductive layer on the spacer layer and on the walls and bottom of the via, spinning-on a photo-definable material on the conductive layer, forming a fill layer on the conductive layer and filling the via, exposing portions of the fill layer to an exposing light using a photomask, developing the fill layer to remove select portions of the fill layer and leave a portion of the fill layer filling the via, and removing the spacer layer. The use of a spin-on photo-definable material increases the material's filling and planarizing capabilities, while enabling a reduction in the number of process steps, which may reduce the likelihood of manufacturing defects, thereby increasing manufacturing yield.

Abstract translation: 用于在集成电路中填充过孔的系统和方法优选实施例包括在衬底上形成间隔层，在间隔层中形成具有壁和底部的通孔，在间隔层上以及在隔离层的壁和底部上沉积共形导电层 所述通孔在所述导电层上旋转可光学定义的材料，在所述导电层上形成填充层并填充所述通孔，使用光掩模将所述填充层的部分暴露于曝光光，显影所述填充层以除去选择 填充层的部分并留下填充层的填充层的一部分，并且去除间隔层。 使用旋涂光可定义材料增加了材料的填充和平面化能力，同时能够减少工艺步骤的数量，这可能降低制造缺陷的可能性，从而提高制造产量。

公开(公告)号：US06884729B2

公开(公告)日：2005-04-26

申请号：US10193589

申请日：2002-07-11

Applicant: Jui-Kun Lee ,  Chris C. Yu ,  David G. Mikolas

Inventor： Jui-Kun Lee ,  Chris C. Yu ,  David G. Mikolas

IPC: B81C1/00 ,  H01L21/302

CPC classification number: B81C1/00611 ,  B81C2201/0123

Abstract: Methods for manufacturing substrates with difficult to polish features using reverse mask etching and chemical mechanical planarization techniques.

Abstract translation: 使用反掩模蚀刻和化学机械平面化技术制造具有难以抛光特征的基板的方法。

公开(公告)号：JP2018158438A

公开(公告)日：2018-10-11

申请号：JP2018040502

申请日：2018-03-07

Applicant: ロベルト・ボッシュ・ゲゼルシャフト・ミト・ベシュレンクテル・ハフツング ,  ROBERT BOSCH GMBH

Inventor： ベンヤミーン・シュトイアー ,  クリストフ・シェリング ,  ダニエル・パンテル ,  シュテファン・ピンター

IPC: B81B1/00 ,  B81C1/00

CPC classification number: B81C1/00626 ,  B81C2201/0123 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2201/053 ,  G02B26/0833

Abstract: 【課題】傾斜した表面を備える微小機械装置の製造方法および対応する微小機械装置を提供する。 【解決手段】前面(OS)の第1垂線(N)が、シリコン基板の〈111〉方向から第1角度(α)だけずれたシリコン基板(1)を準備し、前面に第1溝と第2溝を形成する。第1溝と第2溝は上記ずれの方向に沿って延在し、かつ第1溝および第1溝が実質的に平行に離間している。第1溝と第2溝との間に位置する第1開口範囲(OE)を除いて前面を覆うエッチングマスク(M)を形成し、エッチングマスクを使用して前面に異方性エッチングプロセスを実施し、第1垂線に対して第1角度(α)にほぼ相当する第2角度をなす傾斜した表面を開口範囲(OE)に形成するステップを含む。 【選択図】図2d

公开(公告)号：JP2006066474A

公开(公告)日：2006-03-09

申请号：JP2004244420

申请日：2004-08-24

Applicant: Matsushita Electric Ind Co Ltd ,  松下電器産業株式会社

Inventor： TERANISHI SHINICHI

IPC: H01L21/027 ,  B81C99/00 ,  G03F1/54 ,  G03F7/20 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L27/14

CPC classification number: B81C1/00611 ,  B81C2201/0123

Abstract: PROBLEM TO BE SOLVED: To provide a production process for facilitating machining on the surface of a workpiece in following process by planarizing protrusions and recesses on the surface of the workpiece, e.g. a semiconductor substrate or a micromachine, being subjected to micromachining easily with higher planarity as compared with prior art even when the depth of the recesses is different. SOLUTION: The production process for facilitating machining on the surface in following process by planarizing protrusions and recesses on the surface of a workpiece 1 comprises a step for coating the surface with photosensitive resin 2, a step for exposing the photosensitive resin using a gray scale mask 3 corresponding to the surface profile of the photosensitive resin coating, and a step for developing exposed photosensitive resin and removing uncured photosensitive resin (shaded portion). COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过平面化工件表面上的突起和凹部来促进在后续工艺中在工件表面上的加工的生产方法，例如， 半导体衬底或微机械，即使当凹部的深度不同时，与现有技术相比，也可以更高的平面度地进行微加工。 解决方案：通过平面化工件1的表面上的突起和凹部，在随后的工艺中促进表面的加工的生产工艺包括用感光树脂2涂覆表面的步骤，使用 对应于感光性树脂涂层的表面轮廓的灰度掩模3，以及曝光的感光性树脂显影步骤和去除未固化的感光性树脂（阴影部分）的步骤。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：KR1020150014982A

公开(公告)日：2015-02-09

申请号：KR1020147035824

申请日：2013-05-21

Applicant: 바스프 에스이

Inventor： 리유주오 ,  놀러바슈티안마르텐 ,  길로크리스토쁘 ,  프란츠디아나

IPC: C09K3/14 ,  H01L21/321 ,  H01L21/306 ,  C09G1/02

CPC classification number: C09G1/02 ,  B81C2201/0121 ,  B81C2201/0123 ,  B81C2201/0126 ,  H01L21/02024 ,  H01L21/302 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/461 ,  C09K3/1454

Abstract: 반도체 디바이스들의 제조 방법으로서
화학 기계 연마 조성물 (Q1) 의 존재하에서 적어도 하나의 III-V 재료를 함유하는 기판 또는 층을 화학 기계 연마하는 단계를 포함하고, 상기 화학 기계 연마 조성물 (Q1) 은
(A) 무기 입자들, 유기 입자들 또는 이들의 혼합물 또는 복합물,
(B) 적어도 하나의 양친매성 (amphiphilic) 비이온 계면활성제로서
(b1) 적어도 하나의 소수성 기; 및
(b2) 폴리옥시알킬렌 기들로 이루어지는 군으로부터 선택된 적어도 하나의 친수성 기를 갖고 상기 폴리옥시알킬렌 기들은
(b22) 옥시에틸렌 모노머 단위들 외의 옥시알킬렌 모노머 단위들을 포함하는,
상기 적어도 하나의 양친매성 비이온 계면활성제; 및
(M) 수성 매질
을 포함하는, 반도체 디바이스들의 제조 방법.

公开(公告)号：TWI596174B

公开(公告)日：2017-08-21

申请号：TW102118277

申请日：2013-05-23

Applicant: 巴地斯顏料化工廠 ,  BASF SE

Inventor： 李玉宙 ,  LI, YUZHUO ,  諾勒 巴斯汀 馬汀 ,  NOLLER, BASTIAN MARTEN ,  吉洛特 克里斯多夫 ,  GILLOT, CHRISTOPHE ,  法蘭茲 黛安娜 ,  FRANZ, DIANA

IPC: C09G1/02 ,  H01L21/304

CPC classification number: C09G1/02 ,  B81C2201/0121 ,  B81C2201/0123 ,  B81C2201/0126 ,  H01L21/02024 ,  H01L21/302 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/461