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    高效散热电路板
    31.
    发明申请
    高效散热电路板 审中-公开

    公开(公告)号：WO2008141500A1

    公开(公告)日：2008-11-27

    申请号：PCT/CN2007/003642

    申请日：2007-12-18

    Applicant: 黄虎钧

    Inventor： 黄虎钧

    IPC: H01L25/075 ,  H01L33/00 ,  H01L23/485 ,  H01G2/06

    CPC classification number: H05K1/0206 ,  H01G2/06 ,  H01G2/08 ,  H01L2924/0002 ,  H05K2201/09345 ,  H05K2201/09481 ,  H05K2201/09781 ,  H05K2201/10106 ,  H01L2924/00

    Abstract: A circuit board for heat dispersion includes a rectangle dielectric layer (10) and a plurality of pad groups (1, 2, 3) for soldering an electronic element. The pad groups (1, 2, 3) are laid on the front surface of the dielectric layer (10). Each pad group comprises a plurality of metal conductive pads (11, 12, 13), (21, 22, 23), (31, 32, 33) which are arranged at intervals. There is a first transverse insulating isolated area (6) between the two adjacent pads (11, 12), (12, 13), (21, 22), (22, 23), (31, 32), (32, 33). The width of the insulating isolated area (6) is less than the span between the positive terminal solder area and the negative terminal solder area of the electronic component. There are an anode soldering sheet (7) and a cathode soldering sheet (8) on the back surface of the dielectric layer (10). The anode soldering sheet (7) and cathode soldering sheet (8) spread on the back surface of the dielectric layer (10). There is a second insulating isolated area (9) between the anode soldering sheet (7) and the cathode soldering sheet (8). The first pad (11, 21, 31) and the last pad (13, 23, 33) of each pad group have vias (111, 131), (211, 231), (311, 331). The wall of the vias have conductive plating layer. The plating layer connects the pads to the anode soldering sheet (7) or the cathode soldering sheet (8).

    信号伝送装置及び画像形成装置
    34.
    发明专利
    信号伝送装置及び画像形成装置 审中-公开

    公开(公告)号：JP2018038015A

    公开(公告)日：2018-03-08

    申请号：JP2016172234

    申请日：2016-09-02

    Applicant: 富士ゼロックス株式会社

    Inventor： 坪田 浩和 ,  石井 努 ,  浜田 勉

    IPC: G03G21/00 ,  G03G15/00 ,  G03G21/16 ,  H04B3/56

    CPC classification number: G03G15/5087 ,  G03G15/04045 ,  G03G15/80 ,  G03G21/1652 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/115 ,  H05K1/116 ,  H05K2201/09254 ,  H05K2201/09345 ,  H05K2201/09718

    Abstract: 【課題】インピーダンスを整合させるための回路や素子を用いなくてもインピーダンスの不整合を抑制することができる信号伝送装置及び画像形成装置を提供する。 【解決手段】信号伝送装置は、コントローラ基板260の第1層に形成され、電力を供給する複数の電力線のうち一対の電力線に差動信号を重畳させて伝送する一対の第1の線路14と、一対の第1の線路14に一対の電力線が結合するとともに、結合部15を介して分岐され、第1層とは異なる他の層に形成された複数対の第2の線路16と、第1層と他の層との間に形成されたグランド層17とを備え、グランド層17は、平面視において結合部15を内側に含むように開口17aが形成され、結合部15は、第1の線路14の幅よりも広い幅の結合線路150と、結合線路150と第2の線路16とをグランド層17の開口17aを介して接続するスルーホール151とを備える。 【選択図】図2

    Spurious electromagnetic radiation suppression circuit and its mounting structure, and electronic equipment mounted therewith
    36.
    发明专利
    Spurious electromagnetic radiation suppression circuit and its mounting structure, and electronic equipment mounted therewith 有权
    有机电磁辐射抑制电路及其安装结构及电子设备安装

    公开(公告)号：JP2008060435A

    公开(公告)日：2008-03-13

    申请号：JP2006237160

    申请日：2006-09-01

    Applicant: Hitachi Ltd ,  株式会社日立製作所

    Inventor： FUNATO HIROKI ,  SUGA TAKU

    IPC: H05K1/02 ,  H05K9/00

    CPC classification number: H05K9/0039 ,  H05K1/0215 ,  H05K1/0231 ,  H05K1/116 ,  H05K3/325 ,  H05K3/429 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10409

    Abstract: PROBLEM TO BE SOLVED: To solve the problem that any spurious electromagnetic radiation is newly generated in a case body level in such a stage that a circuit board is mounted on the case body when EMC measures of the circuit board are completed.
    SOLUTION: This circuit board is provided with a power source mounted on electronic equipment or the like and GND, and the GND of the circuit board is electrically connected to the GND of the other configuring elements of the electronic equipment by a connection component, and components or a circuit for achieving low impedance in a target frequency range are arranged between the opening peripheral conductor of a connection port to be used for the connection and the power source of the circuit board.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 解决的问题：为了解决当电路板的EMC测量完成时，在电路板安装在壳体上的阶段中，在壳体水平中新产生任何杂散电磁辐射的问题。 解决方案：该电路板设置有安装在电子设备等上的电源和GND，并且电路板的GND通过连接部件电连接到电子设备的其它配置元件的GND 并且在用于连接的连接端口的开口外围导体和电路板的电源之间设置用于在目标频率范围内实现低阻抗的部件或电路。 版权所有（C）2008，JPO＆INPIT

    Circuit board and semiconductor device with the same, memory module, memory system, and method of manufacturing circuit board
    38.
    发明专利
    Circuit board and semiconductor device with the same, memory module, memory system, and method of manufacturing circuit board 审中-公开
    具有该电路板的电路板和半导体器件，存储器模块，存储器系统以及制造电路板的方法

    公开(公告)号：JP2011049216A

    公开(公告)日：2011-03-10

    申请号：JP2009194143

    申请日：2009-08-25

    Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

    Inventor： HARASHIMA SHIRO

    IPC: H05K1/11 ,  H01L23/12 ,  H05K1/02 ,  H05K1/14 ,  H05K3/40

    CPC classification number: H05K1/117 ,  H01R12/721 ,  H05K1/0263 ,  H05K1/0298 ,  H05K3/0052 ,  H05K3/403 ,  H05K2201/09172 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09345

    Abstract: PROBLEM TO BE SOLVED: To increase a width and a pitch of board terminals provided on a principal surface of a circuit board by decreasing the number of the board terminals.
    SOLUTION: The circuit board includes: the principal surface 100a; a reverse surface 100b parallel with the principal surface 100a; a side surface 100c positioned between edges of the principal surface 100a and the reverse surface 100b; and board terminals 102 and 101 covering parts of the principal surface 100a and the side surface 100c, respectively. The board terminals are provided on not only the principal surface, but also the side surface of the circuit board, thereby, while the width and pitch of the board terminals are sufficiently secured, the total number of the board terminals can be increased.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：通过减少电路板端子的数量来增加设置在电路板的主表面上的电路板端子的宽度和间距。 电路板包括：主面100a; 平行于主面100a的反面100b; 位于主表面100a和反面100b的边缘之间的侧表面100c; 以及覆盖主表面100a和侧表面100c的部分的板端子102和101。 电路板端子不仅设置在主面上，而且还设置在电路板的侧面上，从而在充分确保电路板端子的宽度和间距的同时，可以增加电路板端子的总数。 版权所有（C）2011，JPO＆INPIT

    Electronic controller
    39.
    发明专利
    Electronic controller 有权
    电子控制器

    公开(公告)号：JP2005101532A

    公开(公告)日：2005-04-14

    申请号：JP2004190076

    申请日：2004-06-28

    Applicant: Denso Corp ,  株式会社デンソー

    Inventor： KANAYAMA MITSUHIRO ,  ITABASHI TORU

    IPC: H02M3/00 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46

    CPC classification number: H02M3/00 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10166

    Abstract: PROBLEM TO BE SOLVED: To effectively reduce noises produced by the switching action of a driving circuit in an electronic controller. SOLUTION: In an electronic controller having a charge pump circuit 45, a dedicated power wiring 1 and a power wiring 3 common to each circuit are connected to the charge pump circuit 45 through a via hole va whose impedance is larger than that of the wiring pattern, and similarly, a dedicated ground wiring 5 and a ground wiring 7 common to each circuit are connected to the circuit 45 through a via hole vb. Further, a condenser C for controlling noise production is connected between a power wiring 2 connecting the via hole va and the power wiring 1, and a ground wiring 6 connecting the via hole vb and the ground wiring 5. Accordingly, a sharp current variation is surely prevented from being produced to the common power wiring 3 and the ground wiring 7 by the switching action of switching devices 12 and 13 of the circuit 45. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：有效地减少由电子控制器中的驱动电路的开关动作产生的噪声。 解决方案：在具有电荷泵电路45的电子控制器中，每个电路共用的专用电源线1和电源线3通过阻抗大于 布线图案和类似地，各电路公用的专用接地布线5和接地布线7通过通孔vb连接到电路45。 此外，在连接通孔va的电力布线2和电力布线1之间连接有用于控制噪声产生的电容器C以及连接通孔vb和接地布线5的接地布线6.因此，尖锐的电流变化是 通过电路45的开关装置12和13的切换动作，可靠地防止对共用电力配线3和接地配线7产生。（C）2005，JPO＆NCIPI

    회로 기판 및 이를 포함하는 반도체 모듈
    40.
    发明公开
    회로 기판 및 이를 포함하는 반도체 모듈 无效
    电路板和半导体模块，包括它们

    公开(公告)号：KR1020120026870A

    公开(公告)日：2012-03-20

    申请号：KR1020100089045

    申请日：2010-09-10

    Applicant: 삼성전자주식회사

    Inventor： 김용훈 ,  김현기 ,  이희석

    IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46 ,  H02S50/10

    CPC classification number: H05K1/0231 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/4608 ,  H05K2201/09345 ,  H05K2201/10015 ,  H02S50/10 ,  H01L2924/00014

    Abstract: PURPOSE: A circuit board and a semiconductor module including the same are provided to prevent processing and technical problems generated while forming via patterns by directly connecting a capacitor to metal cores. CONSTITUTION: A core unit(C) comprises a first metal core(122a), a second metal core(122b), top and bottom insulating layers(126a,126b). The first metal core passes through an extension direction of the core unit. The second metal core passes through the extension direction of the core unit. One side of the second metal core is arranged while facing one side of the first metal core. A second capacitor(130) is arranged between the first and second metal cores. The second capacitor comprises a first electrode(133a), a second electrode(133b), and a dielectric layer(131) between the first and second electrodes.

    Abstract translation: 目的：提供一种电路板和包括该电路板的半导体模块，以通过将电容器直接连接到金属芯来防止在形成通孔图案时产生的处理和技术问题。 构成：核心单元（C）包括第一金属芯（122a），第二金属芯（122b），顶部和底部绝缘层（126a，126b）。 第一金属芯通过芯单元的延伸方向。 第二金属芯通过芯单元的延伸方向。 第二金属芯的一侧被布置成面向第一金属芯的一侧。 第二电容器（130）布置在第一和第二金属芯之间。 第二电容器包括在第一和第二电极之间的第一电极（133a），第二电极（133b）和介电层（131）。

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