COMPUTER SYSTEM AND METHOD FOR OPERATION OF BUS INTERFACE DEVICE

    公开(公告)号:JPH0883236A

    公开(公告)日:1996-03-26

    申请号:JP12118895

    申请日:1995-05-19

    Abstract: PURPOSE: To reduce the space of a circuit and an on-chip for address decoders by integrating the address decoders to one location. CONSTITUTION: When a processor starts a given local bus cycle, the processor asserts an address to an address bus to inform of the start of the local bus cycle. Decode logics within a memory controller 504 and an input/output controller 506 decide whether addresses are respectively directed to an memory or an input/output address space. If they are directed, each controller asserts a it signal and informs a bus interface 510 that a present cycle is directed to a device in a CPU local bus 508 and that the bus interface device should not start an external PCT bus cycle.

    METHOD AND SYSTEM FOR GENERATION OF TEST VECTOR

    公开(公告)号:JPH0863367A

    公开(公告)日:1996-03-08

    申请号:JP13401495

    申请日:1995-05-31

    Abstract: PURPOSE: To provide a test vector generation system which generates a test vector to test the coincidence of floating point calculation execution examples. CONSTITUTION: A test vector generation system controls a processor 110 having an exemplary floating point function unit 160 which carries out an exemplary floating point instruction set. Then the system contains a computer program module which includes an interactive test selection process where a test instruction is selected from the instruction set, an operand data generation process, a test instruction execution process where an exemplary function unit executes a test instruction to calculate the generated operand data, and a test vector result recording process where the test vector result of the test instruction execution is recorded.

    PROCESSOR CONTAINING CLOCK GENERATOR AND METHOD FOR TESTING OF DELAY CHAIN

    公开(公告)号:JPH0850574A

    公开(公告)日:1996-02-20

    申请号:JP4973695

    申请日:1995-03-09

    Abstract: PURPOSE: To provide a test structure which contains a variable control delay element and its method. CONSTITUTION: During a normal operation, multiplexers 202A to D inserted in a delay chain 104 are constructed so that plural variable delay units 106A to D are electrically and serially connected with one another. An external command signal to start a test operation where the units 106A to D are tested for predictable defect is given to a microprocessor. During the test operation, a control unit selects the multiplexers 202A to D so that four units 106A to D may be electrically disconnected from one another. Common test signals are simultaneously driven through more than two units 106A to D, and whether the transition of common pulse signals are transmitted substantially at the same time through each unit 106A to D by means of a comparator which is associated with output of each unit 106A to D.

    ELECTRIC POWER CONTROL SYSTEM FOR COMPUTER SYSTEM

    公开(公告)号:JPH0836445A

    公开(公告)日:1996-02-06

    申请号:JP1226195

    申请日:1995-01-30

    Abstract: PURPOSE: To provide a power managing unit in which the power consumption amounts of the overall system can be minimized, even when malfunctioning software is loaded in a computer system. CONSTITUTION: A power control unit 122 and a clock control unit 124 are respectively constituted, dependent on the state of a power managing unit 120, so that a power can be applied or removed to or from a certain specific component in a computer system, and the frequencies of both a CPU clock signal and a system clock signal can be increased or decreased. The power managing unit 120 includes a software constitution enabling state register 136 for allowing system softward, such as software for an advanced power management(APM) in a system BIOS to control the state of the power managing unit. Therefore, the AMP software is applied for controlling the state of the power managing unit.

    SYSTEM FOR SELECTIVELY ENABLING INTERMEDIATE DATA PROCESSINGOF DIGITAL SIGNAL OUTSIDE INTEGRATED CIRCUIT

    公开(公告)号:JPH088845A

    公开(公告)日:1996-01-12

    申请号:JP1261695

    申请日:1995-01-30

    Abstract: PURPOSE: To provide a controller in which design of a new controller by every change of a data processing method is unnecessitated and which is designed not to depend on internal data processing ability very much. CONSTITUTION: An intermediate data processing of a digital signal outside an integrated circuit is selectively made possible by a system 10 and a transcoder 101, a codec 102 connected to the transcoder 101 and a data processor located outside time IC are included in the system 10. The digital signal is switched between the transcoder 101 and the codec 102 by responding to a strobe signal and transmitted to a data route of an external processor by a programmable switch. The digital signal is formatted in the IC and processed by the external processor. The digital signal which is processed outside is returned from the external processor to the IC with the data route. After that, the digital signal is formatted again in the IC and further processed by the IC.

    INCREMENT-ELECTRIC-CURRENT GENERATING CIRCUIT TO DEVELOP OUTPUT CURRENT

    公开(公告)号:JPH086655A

    公开(公告)日:1996-01-12

    申请号:JP8408495

    申请日:1995-04-10

    Inventor: AN UU

    Abstract: PURPOSE: To speed up the turn off time of an external circuit by depending on an input voltage level and generating increment output source current which is previously decided in terms of increment by means of the value of established reference current. CONSTITUTION: Reference current is amplified by a current amplification means 18. The group of voltage reference points is established by a voltage reference means 24 in a state where sufficient current is given by a current amplification means 18. Then, the lump value of input voltages is compared with the voltage reference point in a comparator means 28 whose output flags the highest voltage reference value which input voltage exceeds. The output of the comparator 28 triggers the previously decided increment current part of reference voltage in a current output means 32. The increment current is outputted as output current 36. Then, increment output source current which is previously decided in terms of increment is generated by the value of established reference current.

    CIRCUIT AND METHOD FOR POWER MANAGEMENT IN CLOCK-OR BATTERY-DRIVEN DEVICE

    公开(公告)号:JPH07327326A

    公开(公告)日:1995-12-12

    申请号:JP1613695

    申请日:1995-02-02

    Abstract: PURPOSE: To achieve a battery protection and a sleep synchronous control efficiently at a low cost in a battery-driven device. CONSTITUTION: A power management circuit 10 for a battery-driven device is designed, such that sleeps is induced during a predetermined period when the device is not used, has an oscillator 12 for generating a clock signal, and has a battery monitor sub-circuit 14 for indicating when a predetermined low battery power state is reached, which includes a sub-circuit that allows the oscillator to generate a clock signal and a sub-circuit that responds to an instruction that the predetermined low battery state has been reached from a battery monitor sub-circuit. The sub-circuit interrupts the operation of the sub-circuit, that allows the oscillator to generate a clock signal.

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