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公开(公告)号：DE69818239D1
公开(公告)日：2003-10-23
申请号：DE69818239
申请日：1998-01-21
Applicant: CANDESCENT INTELLECTUAL PROP
Inventor： DRUMM M
Abstract: A method for forming a planar aluminum layer in a flat panel display structure. In one embodiment, the present invention creates a flat panel display structure having a raised black matrix defining wells within the matrix. The present embodiment then deposits a non-conformal layer of acrylic-containing aluminizing lacquer over a layer of phosphors residing within the wells of the black matrix. In so doing, the lacquer layer forms a substantially planar surface on top of the phosphors. The present invention then deposits a layer of catalyst material over the layer of lacquer so that the aluminizing lacquer can be burned off completely and cleanly at a relatively low temperature. The catalytic layer conforms to the planar surface of the lacquer layer. The present invention then deposits an aluminum layer over the catalytic layer. The aluminum layer, in turn, conforms to the planar surface of the catalytic layer. Finally, the present invention bakes off the non-conformal lacquer layer. The baking process is conducted at a temperature such that the lacquer layer is cleanly and completely oxidized. This temperature is relatively low so as not to adversely affect the reflectivity of the aluminum layer, damage the black matrix material, or induce oxidation of phosphors. After the baking process, the present invention achieves a substantially planar and mirror-like aluminum surface.
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公开(公告)号：AU2002343420A1
公开(公告)日：2003-04-07
申请号：AU2002343420
申请日：2002-09-24
Applicant: CANDESCENT INTELLECTUAL PROP
Inventor： FRIEDMAN JAY , HANSEN RONALD L
Abstract: The present invention provides a method and circuit to efficiently change a present column voltage output level to a desired next column voltage output level using digital control circuitry. In one embodiment, the present column voltage output level at an intersection of an active row line and a column line is stored. In substantially the same time, a desired next column voltage level is received for the next row data line of the same column line. The difference between the present column voltage and the desired next voltage is determined and digitized. The digitized voltage difference is translated to a clock time necessary to apply a high current to column driver to attain the desired next column voltage level. The circuit providing high current is active only for the clock time. In this way, bias current and power dissipation are maintained at a low level during quiescent conditions. A quiescent current is continuously applied to all pixels for maintaining their gray cale levels thus compensating for leakage current.
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公开(公告)号：DE69835013T2
公开(公告)日：2007-01-11
申请号：DE69835013
申请日：1998-05-26
Applicant: CANDESCENT INTELLECTUAL PROP
Abstract: An electron-emitting device utilizes an emitter electrode (12) shaped like a ladder in which a line of emitter openings (18) extend through the electrode. In fabricating the device, the emitter openings can be utilized to self-align certain edges, such as edges (38C) of a focusing system (37), to other edges, such as edges (28C) of control electrodes (28), to obtain desired lateral spacings. The self-alignment is typically achieved with the assistance of a backside photolithographic exposure operation. The ladder shape of the emitter electrode also facilitates the removal of short-circuit defects involving the electrode.
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公开(公告)号：DE69334065D1
公开(公告)日：2006-11-09
申请号：DE69334065
申请日：1993-04-08
Applicant: CANDESCENT INTELLECTUAL PROP
Inventor： LOVOI A
IPC: H01J29/70 , B26F1/26 , H01J3/02 , H01J9/14 , H01J9/18 , H01J17/49 , H01J29/02 , H01J29/08 , H01J29/24 , H01J29/46 , H01J31/12 , H01J61/30
Abstract: A grid which controls electron flow, placed between a field emitter cathode and fluorescent anode in a flat cathode ray tube improves focusing, and reduces the switching voltage necessary to stop electron flow. The focusing capabilities of the grid enable increased distance between the cathode and anode, permitting higher anode voltage and use of more efficient phosphors. With the grid, electron flow on/off addressing can be done with drivers operating at less than 30 V, thereby reducing capacitive power loss over prior art addressable arrays and permitting use of inexpensive CMOS control circuitry. The grid's switching capabilities enable the use of a simplified field emitter cathode structure with resistive gate films which increase emitter reliability, emitter life, and, for cathode ray tube displays, the uniformity of the display.
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公开(公告)号：DE69730734T2
公开(公告)日：2005-09-22
申请号：DE69730734
申请日：1997-12-22
Applicant: CANDESCENT INTELLECTUAL PROP
Inventor： SLUSARCZUK M , HAVEN A , CURTIN J , FAHLEN S
IPC: G02F1/13 , G02F1/1333 , G09F9/00 , H01J5/03 , H01J9/24 , H01J17/16 , H01J29/86 , H01J29/87 , H01J29/94 , H01J31/12 , H01J9/26 , H01J9/385 , H01J9/39
Abstract: A flat-panel device is fabricated by a process in which a pair of plate structures (40 and 42) are sealed along their interior surfaces (40A and 42B) to opposite edges (44A and 44B) of an outer wall (44) to form a compartment. Subsequently, exterior support structure (64) is attached to the exterior surface of one of the plate structures (40) to significantly increase resistance of the compartment to bending. Exterior support structure (66) is normally likewise attached to the exterior surface of the other plate structure (42) after the sealing operation. The compartment is then typically pumped down to a high vacuum through a suitable pump-out port (46) and closed. By providing the exterior support structure at such a relatively late stage in the fabrication process, the need for using spacers to support the device against external forces is eliminated or substantially reduced while simultaneously avoiding severe fabrication difficulties that arise in attaching the exterior support structure before the sealing operation.
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Patent Agency Ranking
公开(公告)号：DE69730333T2
公开(公告)日：2005-09-01
申请号：DE69730333
申请日：1997-06-05
Applicant: CANDESCENT INTELLECTUAL PROP
Inventor： LUDWIG N , HAVEN A , MACAULAY M , SPINDT J , CLEEVES M , KNALL JOHAN
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公开(公告)号：DE69827801D1
公开(公告)日：2004-12-30
申请号：DE69827801
申请日：1998-02-10
Applicant: CANDESCENT INTELLECTUAL PROP
Inventor： PORTER D , CHAKAROVA S , KNALL JOHAN , SPINDT J
IPC: C25F3/02 , B81C1/00 , C25F3/14 , H01J9/02 , C25D5/02 , C25D5/48 , B23H3/00 , H01J1/02 , H01J1/62 , B44C1/22
Abstract: A method for forming a field emitter structure. In one embodiment, the present invention creates a structure having a cavity formed into an insulating layer overlying a first electrically conductive layer. The present invention also creates a second electrically conductive layer with an opening formed above the cavity in the insulating layer. The present embodiment deposits a layer of electron emissive material directly onto the second electrically conductive layer without first depositing an underlying lift-off layer such that the electron emissive material covers the opening in the second electrically conductive layer and forms an electron emissive element within the cavity. The present invention applies a first potential to the first electrically conductive layer, such that the first potential is imparted to the electron emissive element formed within the cavity. The present invention also applies a second potential to the second electrically conductive layer, such that the second potential is imparted to the closure layer of electron emissive material. In the present embodiment, the second potential comprises an open circuit potential. The present invention then exposes the field emitter structure to an electrochemical etchant wherein the electrochemical etchant etches electron emissive material which is biased at the open circuit potential. In so doing, the layer of electron emissive material is removed from above the second electrically conductive layer without etching the electron emissive element formed within the cavity.
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公开(公告)号：DE69730333D1
公开(公告)日：2004-09-23
申请号：DE69730333
申请日：1997-06-05
Applicant: CANDESCENT INTELLECTUAL PROP
Inventor： LUDWIG N , HAVEN A , MACAULAY M , SPINDT J , CLEEVES M , KNALL JOHAN
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公开(公告)号：DE69818239T2
公开(公告)日：2004-07-01
申请号：DE69818239
申请日：1998-01-21
Applicant: CANDESCENT INTELLECTUAL PROP
Inventor： DRUMM M
Abstract: A method for forming a planar aluminum layer in a flat panel display structure. In one embodiment, the present invention creates a flat panel display structure having a raised black matrix defining wells within the matrix. The present embodiment then deposits a non-conformal layer of acrylic-containing aluminizing lacquer over a layer of phosphors residing within the wells of the black matrix. In so doing, the lacquer layer forms a substantially planar surface on top of the phosphors. The present invention then deposits a layer of catalyst material over the layer of lacquer so that the aluminizing lacquer can be burned off completely and cleanly at a relatively low temperature. The catalytic layer conforms to the planar surface of the lacquer layer. The present invention then deposits an aluminum layer over the catalytic layer. The aluminum layer, in turn, conforms to the planar surface of the catalytic layer. Finally, the present invention bakes off the non-conformal lacquer layer. The baking process is conducted at a temperature such that the lacquer layer is cleanly and completely oxidized. This temperature is relatively low so as not to adversely affect the reflectivity of the aluminum layer, damage the black matrix material, or induce oxidation of phosphors. After the baking process, the present invention achieves a substantially planar and mirror-like aluminum surface.
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公开(公告)号：AU2002360248A1
公开(公告)日：2003-05-19
申请号：AU2002360248
申请日：2002-09-25
Applicant: SONY CORP , CANDESCENT INTELLECTUAL PROP
Inventor： KEMMOTSU HIDENORI , LEE JUENG-GIL
Abstract: An embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment provides a method of fabricating a cathode in which the passivation layer and the metallic gate chromium are masked and patterned simultaneously. The method effectuates patterning of the passivation layer as necessary and simultaneously fixes a location for both access spots and inter-pixel electrical isolation areas to chromium constituting the metallic gate. Importantly, the present implementation effectively eliminates a conventionally requisite subsequent metallic gate chromium masking and etching step. Advantageously, this effectively streamlines and economizes cathode fabrication. The present embodiment thus reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. This effectively reduces the unit cost of flat panel CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps.
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