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公开(公告)号:JPH1175390A
公开(公告)日:1999-03-16
申请号:JP18496798
申请日:1998-06-30
Applicant: ST MICROELECTRON INC
Inventor: CARLO BAATEMARA , MENEGOLI PAOLO , BRAMBILLA MASSIMILIANO
Abstract: PROBLEM TO BE SOLVED: To improve a method and equipment for starting the rotation of a rotor in a multi-phase DC motor, by controlling the operation of a three-phase DC motor. SOLUTION: A microcontroller 40 controls drive currents in coils 8, 9, 10 through a serial interface 54, a sequencer 56 and a predriver circuit 58. The microcontroller 40 supplies data from a port 60 to the serial interface 54, and the serial interface 54 generates signals based on the data and supplies the signals to the sequencer 56. The sequencer 56 has a set of 8-bit registers, and each register retains information for giving instructions to the predriver circuit 58 for making driving transistors 13, 14, 15, 16, 18 and 20 to either conducting state or non-conducting state.
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公开(公告)号:JPH1168009A
公开(公告)日:1999-03-09
申请号:JP17556698
申请日:1998-06-23
Applicant: ST MICROELECTRON INC
Inventor: HUNDT MICHAEL , ZHOU TIAO
IPC: H01L23/50 , H01L21/48 , H01L23/495
Abstract: PROBLEM TO BE SOLVED: To provide a lead frame, improved in heat dissipating properties, and a manufacturing method thereof. SOLUTION: This lead frame 40 of a plastic integrated circuit package is manufactured through two steps. The load fingers 42 of the lead frame 40 are formed of a rectangular metal sheet in a first step. In a second step, the die pad 44 of the lead frame 40 is clamped, the lead frame 40 is cut with a pair of engaged punching dies to separate the die pad 44 from the lead fingers 42 of the lead frame 40, and the die pad 44 is separated from the lead fingers 42 and set downward, whereby a horizontal gap is basically prevented from being formed between the lead fingers 42 and the die pad 44. The die pad 44 is set downward from the lead fingers 42, so that a vertical separation is formed between the die pad 44 and the lead fingers 42.
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公开(公告)号:JPH1145944A
公开(公告)日:1999-02-16
申请号:JP15008798
申请日:1998-05-29
Applicant: ST MICROELECTRON INC
Inventor: SMITH GREGORY CLIFFORD , SMITH DANIEL KEITH
IPC: H01L29/78 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L27/088
Abstract: PROBLEM TO BE SOLVED: To form a self-aligned contact easily by providing a side wall spacer during a process for forming an LDD region and then removing the side wall spacer before a device is processed furthermore. SOLUTION: A polysilicon layer is formed and patterned before being etched to form conductive polysilicon electrodes 90, 92. Side wall spacers 86, 88 isolate gate electrodes 60, 62 from interconnection leads 90, 92. A contact to an underlying substrate 40 is isolated from the electrodes 60, 62 only by the thickness of the spacers 86, 88. Consequently, the contact can be brought close to the gate electrodes 60, 62 using a sacrificial layer for the LDD side wall spacer. Since a larger contact region is provided, the contact resistance is decreased or the inter-element interval is shortened resulting in the overall dimensional reduction of the device.
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公开(公告)号:JPH1116914A
公开(公告)日:1999-01-22
申请号:JP10615698
申请日:1998-04-16
Applicant: ST MICROELECTRON INC
Inventor: SIDHWA ARDESHIR J , MELOSKY STEPHEN JOHN
IPC: H01L21/285 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/8249 , H01L23/532 , H01L27/06
Abstract: PROBLEM TO BE SOLVED: To provide a manufacture method in which stress in the forming process of a metallic mutual connection signal line with the thinning of an integrated circuit is relieved and cracks not occur. SOLUTION: An opening 36 is formed by making it pass through an interlayered dielectric layer 34, a Ti/TiN layer 39 is adhered to it, and a tungsten plug 38 is formed in the opening 36. A metal adhered titanium layer 40 is formed on the upper faces of the plug 38 and the Ti/TiN layer 39. Then, an AlCu layer 42 having 0.5% of CuO is adhered on the upper face at 460 deg.C at the speed of about 50 Å/second for required thickness. A TiN antireflection layer 44 is formed on the AlCu layer 42 in a gas atmosphere, where a N2 /Ar ratio is 1.5:1.
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公开(公告)号:JPH10294632A
公开(公告)日:1998-11-04
申请号:JP1163798
申请日:1998-01-23
Applicant: ST MICROELECTRON INC
Inventor: NOTARO JOSEPH , EDWARDS WILLIAM E
Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for shaping the digital waveform of integrated circuit process having no area efficient dielectric capacitor. SOLUTION: The dielectric capacitor is replaced with a 1st linearizing diode D1 and a 2nd diode D2 of waveform shaping circuit, and the respective diodes D1 and D2 have junction capacitances to be changed together with voltages applied cross the diodes D1 and D2. A constant current from a constant current source is supplied to the 1st linearizing diode. A current in inverse proportion to the joint capacitance of 1st linearizing diode D1 is generated at a node formed as the connecting part of the constant current source and the 1st linearizing diode D1. The current at this node is supplied to the 2nd diode D2, and the temporally linearized output voltage of waveform shaping circuit is generated.
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公开(公告)号:JPH10283043A
公开(公告)日:1998-10-23
申请号:JP4913398
申请日:1998-03-02
Applicant: ST MICROELECTRON INC
Inventor: EDWARDS WILLIAM E
Abstract: PROBLEM TO BE SOLVED: To provide high stability without increasing power dissipation by changing the zero of a voltage adjuster and offsetting a changing load pole by an FET transistor when output power supply withdrawn by a load is made to fluctuate by load conditions. SOLUTION: A variable impedance device 7 changes the zero of the voltage adjuster 3 by a corresponding form and offsets the changing load pole. For instance, in the case that a current withdrawn by the load increases, a pole frequency increases as well and the voltage adjuster 3 becomes instable. An increased load current makes it possible to reduce the output voltage by an amplifier 6 and pass though more currents through a path transistor 8. The variable impedance device 7 for receiving a reduced voltage through an input terminal 9 reduces a resistance value. The reduced resistance value of the variable impedance 7 increases the zero of the voltage adjuster 3 and offsets the increasing load pole frequency.
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公开(公告)号:JPH10247663A
公开(公告)日:1998-09-14
申请号:JP35750397
申请日:1997-12-25
Applicant: ST MICROELECTRON INC
Inventor: ANTHONY M CHU
IPC: H01L21/60 , H01L23/08 , H01L23/12 , H01L23/498 , H01L23/50
Abstract: PROBLEM TO BE SOLVED: To make it possible to form a package for integrated circuit use by a method wherein holes are provided in first and second boards formed with a plurality of conductive paths, those holes are aligned with each other and the first board is bonded to the second board using a bonding agent. SOLUTION: A plurality of conductive paths 404b and 404d are formed on first and second boards 415 and 417. Holes 403a to 403e are provided in the boards 415 and 417 and pins 402a to 402e are received in these holes 403a to 403e to bond the board 415 to the board 417 with a bonding agent. The pin 402a is connected with an earth plate under the board 417, the pin 402b is connected with a bonding pad 405b on the board 415, the pin 402c is connected with the earth plate under the board 417 and the pin 402d is connected with a bonding pad 405d on the board 415. Moreover, the pin 402e is connected with the power surface of the board 417.
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48.
公开(公告)号:JP2014116307A
公开(公告)日:2014-06-26
申请号:JP2013249831
申请日:2013-12-03
Inventor: THOMAS STAMM
CPC classification number: H02M3/33515 , H02M1/42 , H02M7/217 , H05B33/0815 , Y02B20/347
Abstract: PROBLEM TO BE SOLVED: To provide an improved LED drive circuit and method for illumination.SOLUTION: A fly-back type switched current regulator includes a primary transformer winding coupled to receive a rectified DC signal derived from an AC signal. A drain of a power transistor is coupled to the primary winding, and a source of the power transistor is coupled to an input of a comparison circuit and a primary transformer winding sense resistor. A control terminal of the power transistor is coupled to an output of the comparison circuit. A capacitor stores a variable reference signal for application at a first capacitor terminal to another input of the differential circuit. The variable reference signal is compared with a winding current signal generated by the sense resistor by the comparison circuit. An injection circuit applies an AC signal derived from the rectified DC signal to a second terminal of the capacitor so as to modulate the stored variable reference signal. The regulator is coupled to drive LEDs.
Abstract translation: 要解决的问题:提供改进的LED驱动电路和照明方法。解决方案:回扫式开关电流调节器包括耦合以接收从AC信号导出的整流DC信号的初级变压器绕组。 功率晶体管的漏极耦合到初级绕组,并且功率晶体管的源极耦合到比较电路和初级变压器绕组检测电阻器的输入端。 功率晶体管的控制端耦合到比较电路的输出端。 电容器存储用于在第一电容器端子处施加到差分电路的另一输入端的可变参考信号。 可变参考信号与由比较电路由检测电阻器产生的绕组电流信号进行比较。 注入电路将从整流后的直流信号得到的交流信号施加到电容器的第二端,以便调制存储的可变参考信号。 调节器耦合到驱动LED。
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公开(公告)号:JP2014087056A
公开(公告)日:2014-05-12
申请号:JP2013211156
申请日:2013-10-08
Inventor: OLEG LOGVINOV
IPC: H04B3/54
CPC classification number: H04B3/54 , H03K2217/00 , H03K2217/0009 , H03K2217/0036 , H04W8/00 , H04W52/00 , H04W88/18 , H04W92/00 , H05B37/0263
Abstract: PROBLEM TO BE SOLVED: To provide improved system and method for a power line modem.SOLUTION: In accordance with one embodiment, a method of operating an electronic system includes: detecting an incoming transmission on a power line; and correcting a switching action of a switching mode power supply bonded with the power line when the incoming transmission is detected. The correcting reduces level of interference generated by the switching mode power supply.
Abstract translation: 要解决的问题:为电力线调制解调器提供改进的系统和方法。解决方案:根据一个实施例,一种操作电子系统的方法包括:检测电力线上的输入传输; 以及当检测到进入的传输时,校正与电力线路接合的开关模式电源的切换动作。 校正减少了由开关模式电源产生的干扰水平。
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公开(公告)号:JP2014072526A
公开(公告)日:2014-04-21
申请号:JP2013197609
申请日:2013-09-24
Applicant: St Microelectron Inc , エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics, Inc. , Internatl Business Machines Corp , インターナショナル ビジネス マシーンズ コーポレイションInternational Business Machines Corporation
Inventor: ZHANG JOHN H , CLEVENGER LAWRENCE A , CARL RADENS , YIHENG XU
IPC: H01L21/768 , H01L23/522
CPC classification number: H01L21/76816 , H01L21/76807 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76897 , H01L23/5226 , H01L23/5283 , H01L23/53295
Abstract: PROBLEM TO BE SOLVED: To provide improved techniques for metal interconnection within an integrated circuit die.SOLUTION: A plurality of metal tracks are formed in three metal layers stacked in an integrated circuit die. A protective dielectric layer is formed around the metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between the metal tracks in the metal layers above and below the intermediate metal layer.
Abstract translation: 要解决的问题:提供用于集成电路芯片内的金属互连的改进技术。解决方案:在集成电路管芯中堆叠的三个金属层中形成多个金属轨道。 在中间金属层的金属轨道周围形成保护电介质层。 保护性介电层用作硬掩模,以在中间金属层上方和下方的金属层中限定金属轨道之间的接触通孔。
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