公开(公告)号：JPH1167621A

公开(公告)日：1999-03-09

申请号：JP21519797

申请日：1997-08-08

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SE SHAKURYU

IPC: G03F7/039 ,  C08G73/00 ,  G03F7/40 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To prevent pattern registration errors and to improve overlay accuracy by forming a gate oxide layer, a conductive layer and a resist layer in sequence by lamination on a substrate and by forming an electrical charge dissipating layer including a specified conductive polymer on the resist layer. SOLUTION: A gate oxide layer is formed on a silicon substrate 10. A conductive layer such as polysilicon is formed on the gate oxide layer and is subjected to patterning for demarcating suitable gate electrodes for use in device manufacture. An electron-beam resist layer 12 is deposited on the conductive layer and an electrical charge dissipating layer 14 including a conductive polymer represented by a formula is deposited on the resist layer 12. In this case, R is acid in the formula. In this way, arising of pattern registration errors can be prevented and the overlay accuracy can be improved.

公开(公告)号：JPH1117170A

公开(公告)日：1999-01-22

申请号：JP944798

申请日：1998-01-21

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SAI MOKIN

IPC: H01L29/78

Abstract: PROBLEM TO BE SOLVED: To solve the problem of irregular reflection by providing a polysilicon layer and a gate comprising a noncrystal layer on the polysilicon layer on a gate structure. SOLUTION: A gate structure has a gate 340 of the double-layer structure. The gate 340 is formed on a silicon oxide layer 310 on a silicon substrate 300 by photoengraving technology. The gate 340 comprises a polysilicon layer 320 and noncrystal silicon layer 330. The noncrystal silicon 330 is formed on the polysilicon layer 320. A silicide layer is formed on the silicon layer 330 by self-aligning silicide process. Thus, the problem of the surface irregular reflection of the light in photoengraving process can be solved, and the formation of a gate pattern can be performed highly accurately.

公开(公告)号：JPH1116847A

公开(公告)日：1999-01-22

申请号：JP15851097

申请日：1997-06-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHA EIFUN

IPC: H01L21/265

Abstract: PROBLEM TO BE SOLVED: To provide a method for preventing defective structure of crystalline lattice generated at the process of ion implantation in a substrate or annealing. SOLUTION: A maximum angle θ between solid phase epitaxial regrowing ends is selected. A projection width of an ion implantation distance Rp into a substrate, a projected standard deviation ΔRp in the direction of a first axis and a projected standard deviation ΔY in the direction of a second axis are determined. An expression t=Rp+cosθ[ (ΔYsinθ) +(ΔRpcosθ) } ] is solved to obtain a minimum thickness t. After a surface layer 146 having the minimum thickness t has formed on the substrate, ion implantation is performed. A well 142 is formed for controlling the shape of the area of implantation.

公开(公告)号：JPH10275867A

公开(公告)日：1998-10-13

申请号：JP19130097

申请日：1997-07-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： ON EIMO

IPC: G11C17/00 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/112

Abstract: PROBLEM TO BE SOLVED: To provide a ROM device in which a source/drain region is insulated from a substrate below the source/drain region by the SOI structure and no leak current flows therebetween. SOLUTION: A source/drain region 50 is insulated from a semiconductor substrate 30 below the source/drain region 50 by an SOI structure, to thereby prevent leak current from bowing therebetween. Failures caused by a diode junction between the semiconductor substrate 30 and the source/drain region 50 is prevented, to thereby improve the operating voltage. The source/drain region 50 of a MOSFET memory cell is formed out of intrinsic amorphous silicon instead of heavily-doped polysilicon. The ROM device manufacturing method is thus quite simplified.

公开(公告)号：JPH10107034A

公开(公告)日：1998-04-24

申请号：JP1196597

申请日：1997-01-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： DER-YUAN UU ,  II CHUN SHEN

IPC: H01L21/285 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To facilitate the patterning of a word line by a method wherein a gate is formed on a substrate to form the first metallic silicide layer on the gate and further to form the second metallic silicide layer having silicon in higher concentration than that of the first metallic silicone layer on the first metallic silicide layer. SOLUTION: A substrate having a gate oxide layer 24 and a polysilicon word line 26 is prepared so as to form a refractory metallic silicide layer i.e., a tungsten silicide is formed on the word line 26. Next, a silicon rich metallic silicide or pure silicon layer 30 is formed on the upper surface of the metallic silicide layer 28. This pure silicon layer 30 has silicon on higher concentration than that of the metallic silicide layer 28. Next, an uppermost oxide layer 32 is formed on the upper part surface of the pure silicon layer 30. Resultantly, the formation of tungsten oxide can be avoided thereby facilitating the patterning of the word line. Furthermore, the surface of the oxide layer can be made smooth.

公开(公告)号：JPH1079490A

公开(公告)日：1998-03-24

申请号：JP9118097

申请日：1997-04-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To widen a charge storage area, without widening the surface of a substrate in such a manner that a trunk conductive member of a charge storage capacitor connected to a transfer transistor has lower and upper trunk layers and an L-letter shaped branch conductive layer is connected to the upper trunk layer. SOLUTION: A first storage electrode 49a and a second storage electrode 49b of a DRAM storage capacitor have lower trunk-polysilicon layers 26a, 26b, upper trunk-polysilicon layers 46a, 46b, and branch polysilicon layers 40a, 40b, respectively. Each of the branch polysilicon layers 40a, 40b has L-shape cross section and has a vertical expanding part which extends toward a top face 11 of a substrate 10 and a horizontal extension part which is in direct contact with the inner face of each of the trunk upper polysilicon layers 46a, 46b. The lower trunk polysilicon layers 26a, 26b, each having a T-shape cross section are in direct contact with drain regions 16a, 16b of the DRAM transfer transistor, respectively.

公开(公告)号：JPH1079475A

公开(公告)日：1998-03-24

申请号：JP9117897

申请日：1997-04-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To increase a charge storage area by providing a transfer transistor having source and drain regions, formed on a substrate, and a tree-type capacitor electrically connected to one of the source and drain regions of the transfer transistor. SOLUTION: A storage electrode has a trunk-shaped polysilicon layer 44, having a substantially T-shaped cross section and a branch-shaped polysilicon layer 38 having a substantially L-shaped cross section. The bottom of the trunk- shape polysilicon layer 44 is electrically connected to a drain region 16 of the transfer transistor of the DRAM cell. Sections of the branch-shaped polysilicon layer 38 extend sideward from a vertical portion and extend downward toward a substrate 10. Next, a dielectric layer 46 is formed over the entire exposed surfaces of the trunk-shaped polysilicon layer 44 and the sections of the branch shaped polysilicon layer 38. Next, a polysilicon layer 48 as an oppositely located electrode to the storage electrodes 44 and 38 is formed over the entire dielectric layer 46.

公开(公告)号：JPH09231693A

公开(公告)日：1997-09-05

申请号：JP3529896

申请日：1996-02-22

Applicant: UNITED MICROELECTRONICS CORP

Inventor： UEIIHIYUN HIYUAN

IPC: G11B20/18

Abstract: PROBLEM TO BE SOLVED: To correct data errors selectively in accordance with the type of an optical disk. SOLUTION: As a method for correcting data errors, first an old data sequence and the incidental old eraser pointer are received from an optical disk drive (first step). Next, the old data sequence and the incidental eraser sequence are decoded, outputting a set of new data sequence and an eraser pointer corrected parameter (second step). After that, on the basis of this set, plural eraser pointers are decided that are incidental to the new data sequence (third step). In addition, this device is so structured as to contain a decoding circuit 210 for performing the first step, logical mapping conversion circuit 220 for performing the second step, and a multiplexer 230 for outputting this logical mapping conversion circuit or selectively outputting the old eraser pointer.

公开(公告)号：JPH08131664A

公开(公告)日：1996-05-28

申请号：JP27363294

申请日：1994-11-08

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHI MAO HIYUAN

IPC: A63H5/04 ,  A63H33/26

Abstract: PURPOSE: To harmonize the generation of sounds with twinkles of diodes, etc., to obtain a true-to-life effect by including a sound/frequency transforming circuit, etc., and modifying the twinkle frequency of the twinkle controller to harmonize it with the volume and mass of the shots, in an integral circuit for shots and twinkles of a toy gun. CONSTITUTION: A sound level/mass detector 10 for detecting the input sound level and mass starts along with the start of a shot synthesizer 50. Different selected signals are outputted from a plurality of frequency selecting output terminals SELA, SELB and inputted to a frequency generator 20. The frequency generator 20 modifies the output frequency in correspondence with the input selecting signals, gets to start along with the start of the shot synthesizer 50, outputs the modified frequency which is inputted to a twinkle controller 60. The twinkle controller 60 modifies the activating frequency in correspondence with the input frequency, with which the various diodes 61-63 connected to the various output terminals modify the twinkle frequency.

公开(公告)号：JP2007149626A

公开(公告)日：2007-06-14

申请号：JP2006031912

申请日：2006-02-09

Applicant: United Microelectronics Corp ,  聯華電子股▲ふん▼有限公司

Inventor： PENG FU-SHENG

IPC: H01J37/317 ,  H01J37/244 ,  H01L21/265

CPC classification number: H01J37/3171 ,  H01J37/304 ,  H01J2237/2443 ,  H01J2237/24542 ,  H01J2237/30483 ,  H01J2237/31703

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for ion-implantation to form an ion-implantation area in a predetermined area of a substrate.
SOLUTION: The method comprises the following steps. First, an ion beam is provided, then, a first sectional shape of the ion beam and a first ion density distribution are detected. Then, a second sectional shape and a second ion density distribution of the ion beam are detected by moving the ion beam along a predetermined scanning path. Then, the predetermined scanning path is adjusted and optimized according to the first sectional shape, the first ion density distribution, the second sectional shape and the second ion density distribution. Then, the ion beam is optimized along the optimized predetermined scanning path to form an ion-implantation area in the predetermined area of the substrate.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于离子注入的方法和装置，以在衬底的预定区域中形成离子注入区域。 解决方案：该方法包括以下步骤。 首先，提供离子束，然后检测离子束的第一截面形状和第一离子密度分布。 然后，通过沿着预定扫描路径移动离子束来检测离子束的第二截面形状和第二离子密度分布。 然后，根据第一截面形状，第一离子密度分布，第二截面形状和第二离子密度分布来调整和优化预定扫描路径。 然后，沿着优化的预定扫描路径优化离子束，以在衬底的预定区域中形成离子注入区域。 版权所有（C）2007，JPO＆INPIT