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公开(公告)号：KR1020090020920A
公开(公告)日：2009-02-27
申请号：KR1020070085559
申请日：2007-08-24
Applicant: 삼성전자주식회사
IPC: H01L21/203
CPC classification number: C23C16/515 , C23C16/45536 , C23C16/45544 , H01J37/32183
Abstract: An apparatus for plasma enhanced atomic layer deposition and a method of forming thin film using the same are provided to prevent self bias effect and improve step difference property of a thin film by generating plasma through applying RF voltage while applying voltage pulse. A PEALD(plasma enhanced atomic layer deposition) apparatus comprises a power source for generating plasma. The power source comprises a first power generator(240a), a second power generator(240b) and a control box(235). The first power generator applies voltage pulse. The second power generator applies RF voltage having frequency which is greater than the voltage pulse. The control box is connected to the first and the second power generators and matches signals generated in the first and the second power generators. The control box can be connected to a shower head(230) for gas supply or a substrate holder(210).
Abstract translation: 提供了一种用于等离子体增强的原子层沉积的装置和使用其形成薄膜的方法，以通过在施加电压脉冲的同时施加RF电压来产生等离子体来防止自偏置效应并提高薄膜的差动特性。 PEALD（等离子体增强原子层沉积）装置包括用于产生等离子体的电源。 电源包括第一发电机（240a），第二发电机（240b）和控制箱（235）。 第一台发电机施加电压脉冲。 第二发电机施加频率大于电压脉冲的RF电压。 控制箱连接到第一和第二发电机并匹配在第一和第二发电机中产生的信号。 控制箱可以连接到用于气体供应的喷头（230）或衬底保持器（210）。
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公开(公告)号：KR1020090017884A
公开(公告)日：2009-02-19
申请号：KR1020070082390
申请日：2007-08-16
Applicant: 삼성전자주식회사
IPC: H01L21/203 , H01L21/205 , H01L27/115 , H01L21/8247
CPC classification number: H01L21/28273 , H01L21/203 , H01L21/205 , H01L45/141
Abstract: A method for manufacturing the film is provided to improve the reliability of semiconductor device by using the free cursor having the same ligand. The free cursor of the first substance is prepared. The free cursor of the second material having the same ligand as the first substance is prepared. The free cursor of the first substance and the free cursor of the second material are mixed to manufacture the thin film(12). The first substance and the second material can belong to the same family or the same cycle on the periodic table. The thin film can be formed by ALD or CVD.
Abstract translation: 提供了制造薄膜的方法，以通过使用具有相同配体的游标光标来提高半导体器件的可靠性。 准备第一物质的游标。 准备与第一物质具有相同配体的第二物质的游标。 将第一物质的自由光标和第二物质的自由光标混合以制造薄膜（12）。 第一种物质和第二种物质可以属于周期表上的同一族或同一周期。 该薄膜可以通过ALD或CVD形成。
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公开(公告)号：KR1020080078511A
公开(公告)日：2008-08-27
申请号：KR1020070084953
申请日：2007-08-23
Applicant: 삼성전자주식회사
Inventor： 이정현 , 아우리브스키,알렉세이브이. , 치모라,안드레이엘.
Abstract: A method for re-configuring keys in a wireless network is provided to increase the efficiency of a network which re-configures keys based on different key management algorithms by comparing the number of the exposed nodes with a predetermined threshold value. A method for re-configuring keys in a wireless network includes the steps of: receiving a key re-configuring message(S165); and re-configuring a mesh key block based on an encrypted session key included in the key re-configuring message(S170). The key re-configuring message includes at least one of the encrypted session key and a key index of the key used in the encryption of the session key. The re-configuring step includes the steps of: decoding the encrypted session key with a key corresponding to the key index; and re-configuring a mesh key block by the calculation of the keys included in the mesh key block and the decoded session key.
Abstract translation: 提供了一种用于在无线网络中重新配置密钥的方法，以通过将暴露节点的数量与预定阈值进行比较来提高基于不同密钥管理算法重新配置密钥的网络的效率。 一种用于在无线网络中重新配置密钥的方法包括以下步骤：接收密钥重新配置消息（S165）; 以及基于包括在密钥重新配置消息中的加密会话密钥重新配置网格密钥块（S170）。 密钥重新配置消息包括加密会话密钥和密钥加密中使用的密钥的密钥索引中的至少一个。 重新配置步骤包括以下步骤：用与密钥索引对应的密钥解密加密的会话密钥; 以及通过计算包含在网格关键块中的密钥和解码的会话密钥来重新配置网格密钥块。
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公开(公告)号：KR1020080064613A
公开(公告)日：2008-07-09
申请号：KR1020070001704
申请日：2007-01-05
Applicant: 삼성전자주식회사
IPC: H01L21/20
CPC classification number: H01L21/28537 , H01L27/1021 , H01L29/861
Abstract: A semiconductor device including polysilicon and a method for fabricating the same are provided to grow easily a stable polysilicon by implementing a TaNx material layer having good adhesion characteristics with the polysilicon. A semiconductor device including polysilicon includes a TaNx material layer and a polysilicon layer formed on the TaNx material layer. A range of X of the TaNx material layer is in 0.5 to 1.5. The polysilicon layer, which is a P-type polysilicon layer(22), includes an N-type polysilicon layer on which the P-type polysilicon layer is formed. The polysilicon layer, which is an N-type polysilicon layer, includes a silicide for forming a Schottky barrier on the N-type polysilicon layer.
Abstract translation: 提供包括多晶硅的半导体器件及其制造方法，通过实施与多晶硅具有良好粘合特性的TaNx材料层，容易地生长稳定的多晶硅。 包括多晶硅的半导体器件包括形成在TaNx材料层上的TaNx材料层和多晶硅层。 TaNx材料层的X的范围为0.5〜1.5。 作为P型多晶硅层（22）的多晶硅层包括形成P型多晶硅层的N型多晶硅层。 作为N型多晶硅层的多晶硅层包括在N型多晶硅层上形成肖特基势垒的硅化物。
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45.发明公开
公开(公告)号：KR1020080055378A
公开(公告)日：2008-06-19
申请号：KR1020060128663
申请日：2006-12-15
Applicant: 삼성전자주식회사
CPC classification number: H04L9/3073
Abstract: A method for generating a public key in an elliptic curve cryptography and a system for executing the same are provided to generate an optimized public key by applying a splitting algorithm to a public key calculated through a private key where sequence length is reduced. A method for generating a public key in an elliptic curve cryptography includes the steps of: transforming a private key in a tau-adic pattern for a triple number having a sign(S401); reducing the sequence length of the private key transformed in the tau-adic pattern by using an elliptic curve, Frobenius mapping, and a characteristic equation(S402); and calculating a public key by joining one point to the private key having the reduced sequence length(S403).
Abstract translation: 提供了一种用于在椭圆曲线密码术中生成公开密钥的方法和用于执行该公钥的系统，以通过将分割算法应用于通过减少序列长度的私钥计算的公钥来生成优化的公钥。 一种用于在椭圆曲线密码术中生成公开密钥的方法包括以下步骤：以具有符号的三重号码的tau-adic模式转换私钥（S401）; 通过使用椭圆曲线Frobenius映射和特征方程来减少在tau-adic模式中转换的私钥的序列长度（S402）; 以及通过将一个点连接到具有减小的序列长度的私钥来计算公开密钥（S403）。
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Patent Agency Ranking
公开(公告)号：KR1020080047911A
公开(公告)日：2008-05-30
申请号：KR1020060117920
申请日：2006-11-27
Applicant: 삼성전자주식회사
IPC: G11B20/18
Abstract: A method and an apparatus for asymmetric error correction are provided to achieve more precise correction by separately accumulating counts corresponding to the level of a sample before and after zero crossing, and accumulating counts corresponding to the polarity of a sample other than the sample before and after zero crossing. A method for asymmetric error correction comprises the steps of: detecting whether zero crossing has occurred(720); detecting counts corresponding to the level of a sample before and after zero crossing(730); detecting counts corresponding to the polarity of a sample except for the sample before and after zero crossing(740); adding a weight to the detected counts(750); accumulating the counts(760); comparing the accumulated value with a predetermined threshold and correcting the asymmetric error based on the result(770).
Abstract translation: 提供了一种用于非对称误差校正的方法和装置，以通过分别累积对应于过零之前和之后的样本电平的计数来实现更精确的校正，并且累积对应于除了样本之前和之后的样本的极性的计数 过零点 一种用于非对称纠错的方法包括以下步骤：检测是否发生过零点（720）; 检测对应于过零之前和之后样品的水平的计数（730）; 检测与过零之前和之后的样品的极性相对应的计数（740）; 对所检测的计数加上重量（750）; 累计（760）; 将累积值与预定阈值进行比较，并根据结果校正非对称误差（770）。
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公开(公告)号：KR100829578B1
公开(公告)日：2008-05-14
申请号：KR1020060117917
申请日：2006-11-27
Applicant: 삼성전자주식회사
CPC classification number: B82B3/0004 , B82B3/0038 , B82Y40/00
Abstract: A metal nanotip having a nano-scaled diameter is provided to realize high resolution and low electric resistance when used as a probe tip of a scanning probe microscope or an emitter tip of a field emission diode. A metal nanotip having a nano-scaled diameter comprises: a seed layer(20) formed of TaN or TiN on a substrate(10); and a metal tip(40) formed on the seed layer and comprising any one selected from the noble metal group consisting of Pt, Pd, Au and Ir, wherein the metal tip has a diameter of 1nm-100nm at the pointed end thereof. The seed layer has a thickness of 2nm-500nm. The metal tip is formed vertically on the top of the seed layer.
Abstract translation: 提供具有纳米级直径的金属纳米尖端，用作扫描探针显微镜或场致发射二极管的发射极尖端的探针尖端时实现高分辨率和低电阻。 具有纳米级直径的金属纳米尖端包括：在衬底（10）上由TaN或TiN形成的晶种层（20）; 以及形成在种子层上的金属尖端（40），其包括选自由Pt，Pd，Au和Ir组成的贵金属组中的任一种，其中金属尖端的尖端具有1nm-100nm的直径。 籽晶层的厚度为2nm-500nm。 金属尖端垂直地形成在种子层的顶部上。
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公开(公告)号：KR1020080034735A
公开(公告)日：2008-04-22
申请号：KR1020060101047
申请日：2006-10-17
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/302
CPC classification number: H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675 , H01L21/32136
Abstract: A method for etching a nickel oxide layer is provided to form a nickel oxide layer having a good profile with a size not greater than a micro size by minimizing thermal damage while avoiding re-deposition of etch byproducts on the lateral surface of an etched structure. A substrate(60) is prepared on which a nickel oxide layer(64) is formed. A mask pattern is formed in a predetermined region of the nickel oxide layer. The nickel oxide layer on the circumference of the mask pattern is removed by using plasma generated from etch gas in which main gas and additive gas are mixed in a predetermined mixture ratio. The mask pattern is removed. The main gas can be at least one kind of gas selected from a group composed of Cl2, BCl3, BBr3, HBr, CF4, C2F6, C4F8, CHF3 and CO.
Abstract translation: 提供蚀刻氧化镍层的方法，以通过最小化热损伤同时避免蚀刻副产物在蚀刻结构的侧表面上的再沉积而形成尺寸不大于微尺寸的良好轮廓的氧化镍层。 制备其上形成有氧化镍层（64）的基板（60）。 在氧化镍层的预定区域中形成掩模图案。 通过使用其中主要气体和添加气体以预定的混合比混合的蚀刻气体产生的等离子体来去除掩模图案圆周上的氧化镍层。 去除掩模图案。 主要气体可以是选自由Cl2，BCl3，BBr3，HBr，CF4，C2F6，C4F8，CHF3和CO组成的组中的至少一种气体。
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公开(公告)号：KR1020080034310A
公开(公告)日：2008-04-21
申请号：KR1020060100386
申请日：2006-10-16
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: G11C13/0011 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/144 , G11C13/0004
Abstract: A resistive RAM with an amorphous solid electrolyte, and a method of operating the same are provided to manufacture the resistive RAM by forming a storage node out of the amorphous solid electrolyte and a diffusion metal layer. A first impurity region(12a) and a second impurity region(12b) are formed on a substrate(11). A gate oxide layer(13) and a gate electrode layer(14) are formed on the substrate. A transistor consists of the first and the second impurity regions and the gate electrode layer. An interlayer dielectric(16) covering the transistor is formed on the substrate. A contact hole(20) exposing the second impurity region is formed on an interlayer dielectric(16). The contact hole is filled with a conductive plug(22). A storage node(S) covering the exposed portion of the conductive plug is formed on the interlayer dielectric. The storage node consists of a lower electrode(30), an amorphous solid electrolyte layer(32) and an upper electrode(34).
Abstract translation: 提供具有非晶体固体电解质的电阻RAM及其操作方法，以通过从无定形固体电解质和扩散金属层形成存储节点来制造电阻RAM。 在基板（11）上形成第一杂质区（12a）和第二杂质区（12b）。 在基板上形成栅氧化层（13）和栅电极层（14）。 晶体管由第一和第二杂质区域和栅极电极层组成。 在基板上形成覆盖晶体管的层间电介质（16）。 在层间电介质（16）上形成露出第二杂质区的接触孔（20）。 接触孔填充有导电塞（22）。 在层间电介质上形成覆盖导电插塞的暴露部分的存储节点（S）。 存储节点由下电极（30），无定形固体电解质层（32）和上电极（34）组成。
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公开(公告)号：KR100803213B1
公开(公告)日：2008-02-14
申请号：KR1020060058095
申请日：2006-06-27
Applicant: 삼성전자주식회사
Abstract: 패턴된 자기기록매체 및 그 제조방법이 개시되어 있다.
이 개시된 패턴된 자기기록매체는 플레이트와, 플레이트 위에 수직으로 형성된 다수의 나노 와이어와; 나노 와이어 위에 형성되며, 나노 와이어에 의해 단차되어 패터닝된 자성층;을 포함한다.
이와 같은 구조는 종래의 자성층을 식각하여 패터닝하는 공정을 생략하여 제조될 수 있으며, 자기 도메인의 크기를 나노 크기로 줄일 수 있고, 나아가 나노 와이어의 크기를 조절함으로써 기록밀도를 조절할 수 있다.
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