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公开(公告)号：KR100268063B1
公开(公告)日：2000-10-16
申请号：KR1019960053781
申请日：1996-11-13
IPC: H01L29/786
Abstract: PURPOSE: A thin film transistor having an area for suppressing a leakage current into a channel is provided to effectively reduce a leakage current in an off operation without an additional process, present the characteristic of an offset gate structure in an off state, operate as a non-offset structure in an on state, reduce the leakage current in larger numbers than that of a transistor composed of an offset structure without reducing the amount of an on current in an on operation than the amount of an on current of a transistor composed of a non-offset structure and operatively delete an offset area so as to have an enough gate driving capacity in a turn-on operation and operatively form the offset area so as to cut off a leakage current in a turn-off operation only. CONSTITUTION: The thin film transistor includes a channel area(12P), a gate insulating film(14), source and drain areas(12P(S),12P(D)) and a transparent gate area. The channel area has an off-set area(12a,12b) in the vicinity of both ends. The gate insulating film is formed on the channel area. The source area is formed to the first adjacent portion on the boundary the off-set area of the channel area. The drain area is formed to the second adjacent portion on the boundary the off-set area of the channel area. The transparent gate area is formed to the same length as the gate insulating film on the upper of the gate insulating and has an opaque film in the vicinity of both ends as a length being vertically opposite to the off-set area.
Abstract translation: 目的：提供一种薄膜晶体管，其具有用于抑制流入沟道的漏电流的区域，以便在没有附加处理的情况下有效地减少关断操作中的漏电流，将偏移栅极结构的特性呈现在断开状态，作为 非偏移结构处于导通状态，从而减小漏极电流大于由偏移结构组成的晶体管的漏电流，而不会减少导通电流导通电流的量，而不是由晶体管的导通电流量 非偏移结构，并且操作地删除偏移区域，以便在接通操作中具有足够的栅极驱动能力并且可操作地形成偏移区域，以便仅在关断操作中切断泄漏电流。 构成：薄膜晶体管包括沟道区（12P），栅极绝缘膜（14），源区和漏极区（12P（S），12P（D））和透明栅区。 通道区域在两端附近具有偏移区域（12a，12b）。 栅极绝缘膜形成在沟道区域上。 源极区域形成在边界上的第一相邻部分，该通道区域的偏移区域。 漏极区域形成在边界上的第二相邻部分，该通道区域的偏移区域。 透明栅极区域形成为与栅极绝缘体的上部的栅极绝缘膜相同的长度，并且在两端附近具有与偏移区域垂直相反的长度的不透明膜。
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公开(公告)号：KR1020000021320A
公开(公告)日：2000-04-25
申请号：KR1019980040336
申请日：1998-09-28
Applicant: 한민구
IPC: H01L21/335
Abstract: PURPOSE: A method for manufacturing an active layer of a thin film transistor and a structure thereof are to improve an electrical characteristic of the thin film transistor. CONSTITUTION: A method for manufacturing an active layer of a thin film transistor comprises the steps of: forming an amorphous silicon film(202) on a substrate(200); irradiating locally a light having an energy enough to change an amorphous silicon into a polycrystalline silicon on the amorphous silicon film; and forming a plurality of polycrystalline silicon regions(210) on the amorphous silicon film at fixed space. The polycrystalline silicon regions have a various shape. The amorphous silicon film and the polycrystalline silicon region are regularly formed to each other at a fixed space and have a mesh form and a honeycomb form.
Abstract translation: 目的：制造薄膜晶体管的有源层的方法及其结构是改善薄膜晶体管的电特性。 构成：制造薄膜晶体管有源层的方法包括以下步骤：在衬底（200）上形成非晶硅膜（202）; 局部照射具有足够能量的光以将非晶硅变成非晶硅膜上的多晶硅; 以及在所述非晶硅膜上以固定空间形成多个多晶硅区域（210）。 多晶硅区域具有各种形状。 非晶硅膜和多晶硅区域以固定的空间相互规则地形成，并且具有网状和蜂窝状。
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公开(公告)号：KR1019970024282A
公开(公告)日：1997-05-30
申请号：KR1019950036347
申请日：1995-10-20
Applicant: 한민구
IPC: H01L29/72
Abstract: 1 청구범위에 기재된 발명이 속하는 기술 분야; 본 발명은 바이폴라 모드 전계 효과 트랜지스터에 관한 것이다.
2. 발명이 해결하려고 하는 기술적 과제; 본 발명은 정상 오프 특성을 가지고 순방향 차단능력이 우수하며 높은 전류 이득 및 우수한 스위칭 특성을 갖는 수평형 바이폴라 모드 전계 효과 트랜지스터를 제공한다.
3. 발명의 해결방법의 요지; 본 발명은 수평형 바이폴라 모드 전계 효과 트랜지스터에 있어서, 제1 도전형의 반도체기판과, 절연층과, 제2도전형의 반도체에피층과, 절연막과, 상기 제2도전형의 제1확산영역과, 상기 제1도전형의 제2확산영역과, 상기 제2도전형의 제3확산영역과, 트렌치와, 상기 트렌치 내부에 전극 물질을 채워 형성한 소오스전극과, 상기 제2확산영역의 상부 표면의 개방된 부분에 전극 물질로서 형성된 게이트전극과, 상기 제3확산영역의 상부 표면의 개방된 부분에 전극 물질로서 형성된 드레인전극을 포함한다.
4. 발명의 중요한 용도; 본 발명은 전력용 소자에 적합하게 사용된다.-
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Patent Agency Ranking
公开(公告)号：KR1019970000471B1
公开(公告)日：1997-01-11
申请号：KR1019930021364
申请日：1993-10-14
IPC: H01L29/786
Abstract: There is provided a liquid crystal display in which a picture is constructed of pixel devices each of which includes a source node serving as a predetermined liquid crystal node. The pixel device includes a voltage line connected to a predetermined voltage supply, a first switching transistor, connected to the voltage line, for forming a current path between a predetermined data line and the liquid crystal node, and second switching transistor, connected to the voltage line, for forming a current path between the data line and liquid crystal node. Accordingly, the pixel device whose current driving performance and capacitance increase is provided to speed up the charging time of current at the source node.
Abstract translation: 提供了一种液晶显示器，其中图像由像素装置构成，每个像素装置包括用作预定液晶节点的源节点。 像素装置包括连接到预定电压源的电压线，连接到电压线的第一开关晶体管，用于形成预定数据线和液晶节点之间的电流路径，以及连接到电压的第二开关晶体管 线，用于在数据线和液晶节点之间形成电流路径。 因此，提供了其当前驱动性能和电容增加的像素装置，以加速源节点处的电流的充电时间。
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公开(公告)号：KR100811998B1
公开(公告)日：2008-03-10
申请号：KR1020060121693
申请日：2006-12-04
Applicant: 삼성에스디아이 주식회사 , 재단법인서울대학교산학협력재단 , 한민구
IPC: H01L29/786
CPC classification number: H01L29/78696 , H01L29/78609 , H01L29/78618 , H01L29/78645
Abstract: A thin film transistor and a flat panel display including the same are provided to reduce effectively a leakage current by reducing kink current, horizontal electric field, and band bending. A semiconductor layer having a width and a length is formed on a substrate(10). The semiconductor layer includes a source region, a first channel region(20a), a first dopoing region(20c), a second channel region, and a drain region(20e). The first width of the first channel region is different from the second width of the second channel region. A gate insulating layer is formed on the semiconductor layer. A gate electrode is formed on the gate insulating layer. The gate electrode includes a first gate electrode(40a) formed at a position facing the first channel region and a second gate electrode(40b) formed at a position facing the second channel region.
Abstract translation: 提供薄膜晶体管和包括该薄膜晶体管的平板显示器，以通过减少扭结电流，水平电场和带弯曲来有效地减少泄漏电流。 在衬底（10）上形成具有宽度和长度的半导体层。 半导体层包括源极区，第一沟道区（20a），第一掺杂区（20c），第二沟道区和漏区（20e）。 第一沟道区的第一宽度与第二沟道区的第二宽度不同。 在半导体层上形成栅极绝缘层。 在栅极绝缘层上形成栅电极。 栅电极包括形成在面向第一沟道区的位置处的第一栅电极（40a）和形成在面向第二沟道区的位置的第二栅电极（40b）。
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公开(公告)号：KR100811997B1
公开(公告)日：2008-03-10
申请号：KR1020060121697
申请日：2006-12-04
Applicant: 삼성에스디아이 주식회사 , 재단법인서울대학교산학협력재단 , 한민구
IPC: H01L29/786
CPC classification number: H01L29/78621 , H01L27/1248 , H01L29/78606
Abstract: A thin film transistor, a method for manufacturing the same, and a flat panel display including the same are provided to form a lightly doped drain structure in a junction part between an active region and source/drain regions by using a sidewall effect. A semiconductor layer(13) includes an active region, source/drain regions, and a lightly doped region. A gate insulating layer(14) and a gate electrode(15) are overlapped on the active region. A first interlayer dielectric(16) is formed on the source/drain regions and the gate electrode. A second interlayer dielectric(17) is formed on the first interlayer dielectric and includes a contact hole for exposing a part of the source/drain regions. Source/drain electrodes(18,19) are connected through the contact hole to the source/drain regions. The amount of the first interlayer dielectric deposited on a sidewall of the gate insulating layer is larger than the amount of the first interlayer dielectric deposited on the source/drain regions.
Abstract translation: 提供薄膜晶体管，其制造方法和包括该薄膜晶体管的平板显示器，以通过使用侧壁效应在有源区域和源极/漏极区域之间的接合部分中形成轻掺杂的漏极结构。 半导体层（13）包括有源区，源极/漏极区和轻掺杂区。 栅极绝缘层（14）和栅电极（15）重叠在有源区上。 在源极/漏极区域和栅极电极上形成第一层间电介质（16）。 第二层间电介质（17）形成在第一层间电介质上，并且包括用于暴露一部分源/漏区的接触孔。 源/漏电极（18,19）通过接触孔连接到源极/漏极区域。 沉积在栅极绝缘层的侧壁上的第一层间电介质的量大于沉积在源极/漏极区上的第一层间电介质的量。
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公开(公告)号：KR100326729B1
公开(公告)日：2002-10-25
申请号：KR1019980036242
申请日：1998-09-03
Applicant: 한민구
IPC: G02F1/136 , G02F1/133 , G02F1/1343
Abstract: 본 발명은 박막 트랜지스터 액정 표시장치의 배선 방법에 관한 것이다. 본 발명에서는, 박막 트랜지스터를 구동시키는 게이트 라인과 데이터 라인을 형성함에 있어서, 상기 게이트 라인과 데이터 라인이 교차되는 영역에 층간절연막 및 유전율이 낮은 공기층을 형성시킨다. 그 결과 배선의 유전용량이 감소되고, 이에 따라 신호지연 문제가 보다 개선되는 효과가 있다.
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公开(公告)号：KR1020020034464A
公开(公告)日：2002-05-09
申请号：KR1020000064780
申请日：2000-11-02
IPC: H01L21/336
Abstract: PURPOSE: A polycrystalline silicon thin-film-transistor(TFT) is provided to effectively control a leakage current and to improve reliability by including an air cavity in the edge of a gate oxide layer, and to form the air cavity while using an isotropic etch process and a process for forming an interlayer dielectric using an atmospheric pressure chemical vapor deposition(APCVD) process by eliminating the need to use an additional mask process. CONSTITUTION: A polycrystalline silicon thin film is formed on a glass substrate on which an oxide layer is deposited. A gate insulation layer has the air cavity formed in the edge of a silicon oxide layer formed on the polycrystalline silicon thin film. A gate, a source and a drain are formed by an ion implantation process.
Abstract translation: 目的：提供多晶硅薄膜晶体管（TFT），以有效地控制泄漏电流并通过在栅极氧化物层的边缘中包括空气腔来提高可靠性，并且在使用各向同性蚀刻时形成空气腔 工艺和使用大气压化学气相沉积（APCVD）工艺形成层间电介质的方法，通过消除使用额外的掩模工艺的需要。 构成：在其上沉积有氧化物层的玻璃基板上形成多晶硅薄膜。 栅绝缘层在形成于多晶硅薄膜上的氧化硅层的边缘形成有空气腔。 通过离子注入工艺形成栅极，源极和漏极。
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