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    MANUFACTURING METHOD OF CIRCUIT STRUCTURE
    41.
    发明申请
    MANUFACTURING METHOD OF CIRCUIT STRUCTURE 有权
    电路结构的制造方法

    公开(公告)号：US20110100543A1

    公开(公告)日：2011-05-05

    申请号：US12783806

    申请日：2010-05-20

    Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: B32B38/10 ,  B32B38/04

    CPC classification number: H05K3/465 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/184 ,  H05K3/421 ,  H05K3/4661 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1056

    Abstract: A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.

    Abstract translation: 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。

    METHOD FOR INSPECTING AND MENDING DEFECT OF PHOTO-RESIST AND MANUFACTURING PROCESS OF PRINTED CIRCUIT BOARD
    43.
    发明申请
    METHOD FOR INSPECTING AND MENDING DEFECT OF PHOTO-RESIST AND MANUFACTURING PROCESS OF PRINTED CIRCUIT BOARD 审中-公开
    印刷电路板耐光性和制造工艺缺陷检测方法

    公开(公告)号：US20070087457A1

    公开(公告)日：2007-04-19

    申请号：US11164855

    申请日：2005-12-08

    Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu

    IPC: H01L21/00

    CPC classification number: H05K3/225 ,  H05K1/0269 ,  H05K3/0032 ,  H05K3/064 ,  H05K2203/013

    Abstract: A method for inspecting and mending defects of photo-resist is provided. It includes the following steps. First, a substrate having at least one film is provided. Then, a patterned photo-resist layer is formed on the film. Next, an optical inspection procedure is performed to inspect whether the patterned photo-resist layer has defects or not. If the patterned photo-resist layer has defects, the defects are classified into gaps and protrusions and then the gaps and the protrusions are positioned. If the patterned photo-resist layer has defects such as gaps, an ink-jet printing method, for example, is performed on the patterned photo-resist layer to fill the gaps up. If the patterned photo-resist layer has defects such as protrusions, a laser method, for example, is performed on the patterned photo-resist layer to remove the protrusions. So the defects of the patterned photo-resist layer can be mended.

    Abstract translation: 提供了一种检查和修补光刻胶缺陷的方法。 它包括以下步骤。 首先，提供具有至少一个膜的基板。 然后，在膜上形成图案化的光致抗蚀剂层。 接下来，执行光学检查程序以检查图案化的光致抗蚀剂层是否具有缺陷。 如果图案的光致抗蚀剂层具有缺陷，则将缺陷分为间隙和突起，然后定位间隙和突起。 如果图案化的光致抗蚀剂层具有诸如间隙的缺陷，则在图案化的光致抗蚀剂层上进行例如喷墨打印方法来填充间隙。 如果图案化的光致抗蚀剂层具有诸如突起的缺陷，则在图案化的光致抗蚀剂层上执行例如激光方法以去除突起。 因此，可以修补图案化光致抗蚀剂层的缺陷。

    Circuit structure of circuit board
    44.
    发明授权
    Circuit structure of circuit board 有权
    电路板的电路结构

    公开(公告)号：US08466369B2

    公开(公告)日：2013-06-18

    申请号：US13305310

    申请日：2011-11-28

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K1/03

    CPC classification number: H05K3/107 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/061 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/0369 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.

    Abstract translation: 电路板的电路结构包括电介质层，多个第一电路和多个第二电路。 电介质层具有表面和凹版图案。 第一电路设置在电介质层的表面上。 第二电路设置在电介质层的凹版图案中。 第二电路的线宽小于第一电路的线宽，并且相邻的第二电路中的每两个之间的距离比相邻的第一电路中的每两个之间的距离短。

    PROCESS FOR FABRICATING WIRING BOARD
    45.
    发明申请
    PROCESS FOR FABRICATING WIRING BOARD 审中-公开
    制造布线板的工艺

    公开(公告)号：US20120174391A1

    公开(公告)日：2012-07-12

    申请号：US13423578

    申请日：2012-03-19

    Applicant: Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

    Inventor： Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

    IPC: H05K3/00

    CPC classification number: H05K3/428 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/20 ,  H05K3/205 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126

    Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.

    Abstract translation: 提供一种制造布线板的工艺。 在该过程中，形成包括携带衬底和布线层的布线承载衬底。 接下来，在布线承载基板中形成至少一个盲孔。 接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。 绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。 接下来，去除部分搬运基板以露出盲孔中的绝缘层。 接下来，形成连接在布线层之间的导电柱。 接下来，其余的携带衬底被去除。

    Embedded wiring board and a manufacturing method thereof
    46.
    发明授权
    Embedded wiring board and a manufacturing method thereof 有权
    嵌入式布线板及其制造方法

    公开(公告)号：US08217278B2

    公开(公告)日：2012-07-10

    申请号：US12613072

    申请日：2009-11-05

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K1/11

    CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

    Abstract: An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.

    Abstract translation: 嵌入布线板包括上布线层，下布线层，绝缘层，第一导电柱和第二导电柱。 上布线层包含上焊盘，下布线层包含下焊盘，绝缘层包含与上表面相对的上表面和下表面。 上垫片嵌入在上表面中，下垫片嵌入下表面。 第一导电柱位于绝缘层中，并且包括由上表面暴露的端面。 第一导电柱相对于上表面的高度大于上垫相对于上表面的深度。 此外，第二导电柱位于绝缘层中并连接在第一导电柱和下垫之间。

    Circuit structure and process thereof
    48.
    发明授权
    Circuit structure and process thereof 有权
    电路结构及其工艺

    公开(公告)号：US07745933B2

    公开(公告)日：2010-06-29

    申请号：US11739515

    申请日：2007-04-24

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

    Abstract: A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via pad disposed on a surface of the first dielectric layer away from the first via pad and connecting to one end of the first conductive via. The circuit structure further has a second dielectric layer disposed over the surface of the first dielectric layer where the independent via pad is disposed, a second conductive via passing through the second dielectric layer and connecting to the independent via pad, and a second circuit pattern embedded in the second dielectric layer, located at a surface thereof away from the independent via pad, and having a second via pad connected to the second conductive via.

    Abstract translation: 电路结构具有第一电介质层，第一电路图案，其嵌入在第一电介质层中并且具有第一通孔焊盘，穿过第一电介质层并连接到第一通孔焊盘的第一导电通孔和设置在第一电介质层上的独立通孔焊盘 在第一电介质层的远离第一通孔焊盘的表面上并连接到第一导电通孔的一端。 电路结构还具有设置在第一电介质层的表面上的第二电介质层，其中设置独立通孔焊盘，通过第二介电层并连接到独立通孔焊盘的第二导电通孔和嵌入的第二电路图案 在第二电介质层中，位于其远离独立通孔焊盘的表面，并且具有连接到第二导电通孔的第二通孔焊盘。

    CIRCUIT STRUCTURE AND PROCESS THEREOF
    50.
    发明申请
    CIRCUIT STRUCTURE AND PROCESS THEREOF 有权
    电路结构及其过程

    公开(公告)号：US20080179744A1

    公开(公告)日：2008-07-31

    申请号：US11739515

    申请日：2007-04-24

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H01L23/48

    CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

    Abstract: A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via pad disposed on a surface of the first dielectric layer away from the first via pad and connecting to one end of the first conductive via. The circuit structure further has a second dielectric layer disposed over the surface of the first dielectric layer where the independent via pad is disposed, a second conductive via passing through the second dielectric layer and connecting to the independent via pad, and a second circuit pattern embedded in the second dielectric layer, located at a surface thereof away from the independent via pad, and having a second via pad connected to the second conductive via.

    Abstract translation: 电路结构具有第一电介质层，第一电路图案，其嵌入在第一电介质层中并且具有第一通孔焊盘，穿过第一电介质层并连接到第一通孔焊盘的第一导电通孔和设置在第一电介质层上的独立通孔焊盘 在第一电介质层的远离第一通孔焊盘的表面上并连接到第一导电通孔的一端。 电路结构还具有设置在第一电介质层的表面上的第二电介质层，其中设置独立通孔焊盘，通过第二介电层并连接到独立通孔焊盘的第二导电通孔和嵌入的第二电路图案 在第二电介质层中，位于其远离独立通孔焊盘的表面，并且具有连接到第二导电通孔的第二通孔焊盘。

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