AN IMPROVED TARGET ASSOCIATION METHOD
    41.
    发明申请
    AN IMPROVED TARGET ASSOCIATION METHOD 审中-公开
    改进的目标协调方法

    公开(公告)号:WO1989009977A1

    公开(公告)日:1989-10-19

    申请号:PCT/US1989000826

    申请日:1989-03-02

    CPC classification number: G06T7/246

    Abstract: An improved target association method including the steps of: a) generating a matrix of cost functions having n rows corresponding to n targets from a first frame of data and m columns corresponding to m targets in a second frame of data, each cost function being either a function of one of n targets in a first frame of data and one of m targets in a second frame of data, or a dummy value; b) ordering the rows of said matrix; c) associating, for each row in accordance with said order of said rows, the target corresponding to the row with the target corresponding to the column, not previously associated, having the smallest cost function so that each target from said first frame of data is optimally associated with a single target in said second frame of data.

    Abstract translation: 一种改进的目标关联方法,包括以下步骤:(a)从图像传感器产生表示目标检测的电信号或光信号; (b)将来自第一检测间隔的信号存储在第一存储器中作为第一数据帧; (c)将来自第二检测间隔的信号存储在第二存储器中作为第二数据帧; (d)从数据的第一帧和与m个目标对应的m列生成对应于n个目标的n行的成本函数矩阵,每个成本函数是第一个数据中的n个目标之一的函数 数据帧,第二帧数据中的m个目标之一; (e)通过以下步骤对矩阵的行进行排序:(i)针对每行计算等于行中两个最小成本函数之间的差的值; (ii)识别并选择具有最大差值的行作为初始起始行,并且从排除考虑用于计算后续行的差值的列,其中行中最小成本函数所在的列; (iii)将所选行设置为顺序中的第一行; (iv)计算后续行的差值; (v)如果该行具有比先前选择的任何行的差值大的差值,则按行提供其余行的最大差值的顺序将下一行设置为下一行,然后重新计算先前选择的行的差异值去除 从计算差值的考虑中,当前所选行中最小成本函数所在的列; (vi)根据差值排序所选行; (vii)如果所选择的行是最后一行,则重复从最后选择的行开始的步骤(iv)至(vi),然后(f)根据行的顺序对于每一行关联来自 对应于具有来自对应于具有最小成本函数的列的对应于该列的目标的信号的行的目标,使得与来自第一数据帧的每个目标相对应的每个信号与对应于单个目标的信号最佳地相关联 在第二帧数据中。

    DELAYED REPLICA RADAR TEST SET TARGET
    42.
    发明申请
    DELAYED REPLICA RADAR TEST SET TARGET 审中-公开
    延迟雷达重复测试设定目标

    公开(公告)号:WO1989008854A2

    公开(公告)日:1989-09-21

    申请号:PCT/US1989000767

    申请日:1989-02-27

    CPC classification number: G01S7/4052 G01S2007/4095

    Abstract: A radar test set target which is co-located with the radar and produces a faithful replica of the radar signal substantially delayed in time. The radar signal modulates a laser light which is controllable delayed in time by transmitting the modulated laser light through a fiber optic delay line. The output of the delay line is demodulated and the extracted and delayed radar signal is returned to the radar as a test signal.

    Abstract translation: 雷达控制装置目标与雷达位于同一位置,并产生雷达信号的忠实复制品,并具有显着的延迟。 雷达信号通过将调制后的激光透过光纤的延迟电路来调制可以延迟时间控制的激光。 延迟电路的输出被解调,并且提取和延迟的雷达信号作为控制信号返回到雷达。

    EXTENDED LIFE NICKEL-HYDROGEN STORAGE CELL
    44.
    发明申请
    EXTENDED LIFE NICKEL-HYDROGEN STORAGE CELL 审中-公开
    延长寿命镍氢储存池

    公开(公告)号:WO1989005525A2

    公开(公告)日:1989-06-15

    申请号:PCT/US1988003359

    申请日:1988-10-03

    CPC classification number: H01M10/26 H01M10/345

    Abstract: A nickel-hydrogen electrical storage cell (10) contains a nickel positive electrode (14), a hydrogen negative electrode (16), a separator (18) between the electrodes (14 and 16), and electrolyte including a rubidium hydroxide and cesium hydroxide, and a pressure vessel to contain these elements. The cell (10) is expected to operate for extended cycle life in deep discharge conditions based upon extrapolations of accelerated life testing results. The electrolyte may be essentially entirely rubidium hydroxide or cesium hydroxide, a mixture of the two, or a mixture with another component. This type of storage cell is useful in spacecraft applications.

    MICROWAVE INTEGRATED DISTRIBUTED AMPLIFIER WITH FIELD EMISSION TRIODES
    45.
    发明申请
    MICROWAVE INTEGRATED DISTRIBUTED AMPLIFIER WITH FIELD EMISSION TRIODES 审中-公开
    MICROWAVE集成分布式放大器与场发射三极管

    公开(公告)号:WO1989004087A1

    公开(公告)日:1989-05-05

    申请号:PCT/US1988002672

    申请日:1988-08-08

    CPC classification number: H03F3/602 H01J1/304 H01J3/021

    Abstract: A microwave distributed amplifier (210) includes a plurality of cascaded field emission triodes (211, 212, 213), each having a field emission element (218) for emitting electrons, a grid (224) disposed downstream from the field emission element (218) along the electron flow path and an anode (243) disposed further downstream along the electron flow path. A series of inductive strips (228) interconnect successive grids (224) to form a grid transmission line (222), while another series of inductive strips (244) interconnect successive anodes (243) to form an anode transmission line (240). Small electron transit times over integrated circuit distances in a vacuum environment and low interelectrode capacitance allow extremely large gain-bandwidth products to be achieved.

    Abstract translation: 微波分布放大器(210)包括多个级联场致发射三极管(211,212,213),每个具有用于发射电子的场致发射元件(218),设置在场发射元件(218)下游的栅极(224) )和沿着电子流动路径设置在更下游的阳极(243)。 一系列感应条(228)互连连续的栅格(224)以形成网格传输线(222),而另一系列的感应条(244)互连连续的阳极(243)以形成阳极传输线(240)。 在真空环境和低电极间电容的集成电路距离上的小电子传输时间允许实现极大的增益带宽产品。

    MONOLITHIC CHANNELING MASK HAVING AMORPHOUS/SINGLE CRYSTAL CONSTRUCTION
    46.
    发明申请
    MONOLITHIC CHANNELING MASK HAVING AMORPHOUS/SINGLE CRYSTAL CONSTRUCTION 审中-公开
    具有不规则/单晶结构的单声道通道

    公开(公告)号:WO1989003544A1

    公开(公告)日:1989-04-20

    申请号:PCT/US1988002961

    申请日:1988-08-30

    CPC classification number: G03F1/22

    Abstract: A mask (18) for use in ion beam and x-ray lithography is prepared by depositing several layers of silicon-based materials onto a polished single-crystal silicon wafer (24), and then etching the layered structure to form the mask (18). A boron-doped, single crystal, epitaxial silicon layer (22) is first deposited overlying the silicon wafer (24), and the boron-doped layer (22) is partially oxidized on its exposed surface to form a thin silicon dioxide layer overlying the boron-doped layer (22). A layer of amorphous silicon is deposited overlying the silicon dioxide layer, an upper layer of silicon nitride is deposited overlying the amorphous silicon, and a lower layer of silicon nitride is deposited overlying the opposite side of the single-crystal silicon wafer (24). After patterning, a window is etched through the lower silicon nitride layer and into the single-crystal silicon wafer (24), to the boron-doped silicon layer (22). The exposure pattern is etched into the membrane through the upper silicon nitride layer, the layer of amorphous silicon, and the silicon dioxide layer, leaving thick unpatterned areas and thin patterned areas. During use of the mask, ions or x-rays pass through the patterned areas of the membrane, but are absorbed in the thicker unpatterned areas, to produce a pattern of transmitted ions or x-rays on the target.

    Abstract translation: 通过在抛光的单晶硅晶片(24)上沉积几层硅基材料,然后蚀刻层状结构以形成掩模(18),制备用于离子束和x射线光刻的掩模(18) )。 首先沉积硼掺杂的单晶,外延硅层(22),覆盖硅晶片(24),并且硼掺杂层(22)在其暴露的表面上被部分氧化以形成薄的二氧化硅层 硼掺杂层(22)。 沉积覆盖二氧化硅层的非晶硅层,沉积覆盖非晶硅的上层氮化硅,并且沉积覆盖在单晶硅晶片(24)的相对侧上的下层氮化硅。 在图案化之后,将窗口通过下部氮化硅层和单晶硅晶片(24)蚀刻到掺杂硼的硅层(22)上。 曝光图案通过上部氮化硅层,非晶硅层和二氧化硅层蚀刻到膜中,留下厚的未图案区域和薄的图案化区域。 在使用掩模期间,离子或X射线穿过膜的图案化区域,但被吸收在较厚的未图案化区域中,以产生目标上透射离子或X射线的图案。

    METHOD AND APPARATUS FOR SECURING INTEGRATED CIRCUITS FROM UNAUTHORIZED COPYING AND USE
    47.
    发明申请
    METHOD AND APPARATUS FOR SECURING INTEGRATED CIRCUITS FROM UNAUTHORIZED COPYING AND USE 审中-公开
    用于从未经授权的复制和使用中保护集成电路的方法和装置

    公开(公告)号:WO1989003124A1

    公开(公告)日:1989-04-06

    申请号:PCT/US1988001726

    申请日:1988-05-19

    Abstract: A security system and method for IC circuits has at least one additional circuit element that does not contribute toward the IC's circuit function, but inhibits proper functioning of the IC in case of an attempted copying or other unauthorized use. The identity of the additional circuit elements is disguised by forming them with the visible appearance of an apparent element but with a physical modification which is not readily visible but causes them to function in a different manner, by providing different ICs with unique control codes, or both. Physical modifications not readily visible to a copyist include very narrow open circuit cuts in metallized connection lines, preferably with a focused ion beam (FIB) or laser beam; and/or disordering the lattice structure or changing the doping level of a semiconductor region, preferably with an FIB; and/or injecting electrical charge into a semiconductor region, preferably with an electron beam. The additional elements can be formed into a control code subcircuit for the IC, with the code disguised by the use of apparent elements. ICs can be grouped into an operational ring in which control codes are transmitted serially through the ring, and the invention can be applied to a combined hardware/software system. Individual copies of the software, preferably the operating system software, contain the unique control codes required by the modified ICs and the algorithms to interact with the system hardware for the purposes of transmitting, receiving, and authenticating the control codes.

    HIGH-SPEED DIGITAL DATA COMMUNICATION SYSTEM
    48.
    发明申请
    HIGH-SPEED DIGITAL DATA COMMUNICATION SYSTEM 审中-公开
    高速数字数据通信系统

    公开(公告)号:WO1989002201A2

    公开(公告)日:1989-03-09

    申请号:PCT/US1988002865

    申请日:1988-08-19

    CPC classification number: H04L25/02

    Abstract: According to the invention, a high-speed digital data communication system employs current mode circuitry as input and output devices at the ends of a transmission line, such as the interconnections between integrated circuit chips. Specifically, a current mode driver switch generates output current amplitudes responsive to a source of a digital signal representative of data to be transmitted. The switch output is connected to the input of a transmission line. The output of the transmission line is connected to the input of a receiving circuit that responds to the current amplitudes and has an input at an approximately constant voltage level. The receiving circuit is a transistor connected in a common base configuration. The emitter of the transistor is connected to the output of the transmission line. The base of the transistor is connected to a constant voltage source. A pulse shaper in the form of a Schmitt trigger has positive feedback from output to input. The described current mode circuitry is incorporated into an integrated circuit chip.

    SILICON-ON-SAPPHIRE LIQUID CRYSTAL LIGHT VALVE AND METHOD
    49.
    发明申请
    SILICON-ON-SAPPHIRE LIQUID CRYSTAL LIGHT VALVE AND METHOD 审中-公开
    SILICON-ON-SAPPHIRE液晶水晶灯和方法

    公开(公告)号:WO1989001174A1

    公开(公告)日:1989-02-09

    申请号:PCT/US1988002034

    申请日:1988-06-16

    CPC classification number: G02F1/1354

    Abstract: An LCLV is formed with a sapphire substrate (20) base, a highly doped, thin silicon epitaxial layer (2) forming an ohmic back contact on a smooth surface of the sapphire substrate, and a lightly doped, high resistivity silicon epitaxial layer (4) in the range of about 20-60 microns thick on the back contact. The use of a sapphire substrate provides a better surface quality and higher resolution than previously available with the semiconductor substrates. Lattice defects in the thin back contact are reduced by the formation of a buried amorphous layer adjacent the sapphire substrate, and subsequent recrystallization thereof using the unamorphized portions of the back contact as recrystallization seeds. The application of the invention to both MOS and Schottky diode LCLVs is discussed.

    ANALOG-DIGITAL CORRELATOR
    50.
    发明申请
    ANALOG-DIGITAL CORRELATOR 审中-公开
    模拟数字相关器

    公开(公告)号:WO1989000279A2

    公开(公告)日:1989-01-12

    申请号:PCT/US1988002159

    申请日:1988-06-22

    CPC classification number: G01S13/288 G06J1/005

    Abstract: An analog-digital correlator (10) utilizes a plurality of sample and hold circuits (16-0 to 16-(M-1)) to directly store samples of a received analog signal. Bits of a correlation pattern are shifted through stages in a correlation pattern shift register (26). The state of the correlation pattern bits causes the value in the associated sample and hold circuit (16) to either be inverted or noninverted when it is summed with other similarly generated signals from the remaining sample and hold circuits to form the correlation output sum by network (30). The output of network (30) will peak when the bits of the digital correlation pattern signal are shifted to stages in register (26) that are aligned with the sample and hold circuits containing the digitally-impressed code of interest. In the preferred embodiment, a mask shift register (28) is used to selectively disable certain of the sample and hold circuits from affecting the correlation output sum. To this end, mask bits corresponding to the length of the digitally-impressed code are shifted through mask register (28) simultaneously with the correlation pattern bits in register (26).

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