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公开(公告)号：AU2002302830A1
公开(公告)日：2003-01-21
申请号：AU2002302830
申请日：2002-06-18
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , JEFFRIES CLARK DEBS , CALVIGNAC JEAN LOUIS , DAMON PHILIPPE , BASSO CLAUDE , HEDDES MARCO
IPC: G06F17/30
Abstract: A method and system for performing a pattern match search for a data string having a plurality of characters separated by delimiters. In accordance with the method of the present invention a search key is constructed by generating a full match search increment comprising the binary representation of a data string element, wherein the data string element comprises all characters between a pair of delimiters. The search key is completed by concatenating a pattern search prefix to the full match search increment, wherein the pattern search prefix is a cumulative pattern search result of each previous full match search increment. A full match search is then performed within a lookup table utilizing the search key. In response to finding a matching pattern within the lookup table, the process returns to constructing a next search key. In response to not finding a matching pattern, the previous full match search result is utilized to process the data string.
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公开(公告)号：AU2002225237A1
公开(公告)日：2002-11-05
申请号：AU2002225237
申请日：2002-01-28
Applicant: IBM
Inventor： VERPLANKEN FABRICE JEAN , HEDDES MARCO , BASSO CLAUDE , LOGAN JOSEPH FRANKLIN , CALVIGNAC JEAN LOUIS
Abstract: Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.
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公开(公告)号：BR0015717A
公开(公告)日：2002-07-23
申请号：BR0015717
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINSS STEVEN KENNETH , LEAVENS ROSS BODY , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：CA2403193A1
公开(公告)日：2001-10-25
申请号：CA2403193
申请日：2001-03-26
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , VERPLANKEN FABRICE JEAN , SIEGEL MICHAEL STEVEN , HEDDES MARCO , CALVIGNAC JEAN LOUIS
Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars wit h different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
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公开(公告)号：CA2316122A1
公开(公告)日：2001-07-04
申请号：CA2316122
申请日：2000-08-17
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , VERPLANKEN FABRICE JEAN , HEDDES MARCO C , JENKINS STEVEN KENNETH , TROMBLEY MICHAEL RAYMOND , SIEGEL MICHAEL STEVEN , BASS BRIAN MITCHELL
IPC: G06F12/06 , G06F12/00 , G06F12/02 , G06F13/00 , G06F13/16 , G06F15/167 , G11C11/407 , H04L12/56 , G11C7/10
Abstract: The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In on e aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full 'read' and 4 banks of full 'write' by the network processor for every repetition of the DRAM time clock. A scheme for randomized 'read' and 'write' access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variabl e frame sizes.
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Patent Agency Ranking
公开(公告)号：ES2265971T3
公开(公告)日：2007-03-01
申请号：ES00959158
申请日：2000-08-24
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , GALLO ANTHONY MATTEO , HEDDES MARCO C , RAO SRIDHAR , SIEGEL MICHAEL STEVEN
IPC: G06F13/00 , G06F15/16 , G06F13/38 , G06F13/40 , G06F15/00 , G06F15/173 , G06F15/177 , G06F15/76 , H04L12/56
Abstract: Aparato que comprende: un procesador del punto de control; un dispositivo de interfaz conectado operativamente a dicho procesador del punto de control por un camino de control y que proporciona un camino de datos de alta velocidad, teniendo dicho dispositivo de interfaz un substrato (10) de semiconductores; una pluralidad de procesadores (12) del interfaz formados sobre dicho substrato, siendo el número de dichos procesadores al menos cinco; una memoria interna de instrucciones formada sobre dicho substrato y que almacena instrucciones de manera accesible para dichos procesadores del interfaz; una memoria interna de datos formada sobre dicho substrato y que almacena datos que pasan a través de dicho dispositivo, de manera accesible para dichos procesadores del interfaz; y una pluralidad de puertos de entrada/salida formados sobre dicho substrato; conectando al menos uno de dichos puertos de entrada/salida a dicha memoria interna de datos con la memoria externa de datos; intercambiando, al menos otros dos de dichos puertos de entrada/salida, datos que pasan a través del dispositivo de interfaz, con una red externa a la velocidad del medio bajo la dirección de dichos procesadores del interfaz; cooperando dicho procesador del punto de control con dicho dispositivo de interfaz, cargando en el interior de dicha memoria de instrucciones las instrucciones que han de ser ejecutadas por dichos procesadores del interfaz al dirigir el intercambio de datos entre dichos puertos de entrada/salida de intercambio de datos y el flujo de datos a través de dicha memoria de datos.
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公开(公告)号：ES2237667T3
公开(公告)日：2005-08-01
申请号：ES02712095
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , HEDDES MARCO , LOGAN JOSEPH FRANKLIN , VERPLANKEN FABRICE JEAN
IPC: H04L12/861 , H04L29/06 , H04L12/56
Abstract: Un sistema que comprende: - un procesador (100) configurado para tratar cuadros de datos, cuyo procesador comprende: - una unidad (110) de flujo de datos configurada para recibir y transmitir dichos cuadros de datos, y en la que cada uno de dichos cuadros de datos tiene un bloque de control de cuadro asociado, y cada uno de dichos bloques de control de cuadro comprende unos bloques de control primero y segundo; - una primera memoria (210) acoplada a dicha unidad de flujo de datos, cuya primera memoria comprende una primera unidad de control de memoria intermedia de cuadro, y dicha primera unidad de control de memoria intermedia de cuadro almacena información de campo para dicho primer bloque de control de dicho bloque de control de cuadro; y - un planificador de ejecución (130) acoplado a dicha unidad de flujo de datos, cuyo planificador está configurado para planificar cuadros de datos recibidos por dicha unidad de flujo de datos, y en el que dicho planificador comprende una segunda memoria (224), la cual comprende una segunda unidad de control de memoria intermedia de cuadro, y dicha segunda unidad de control de memoria intermedia de cuadro almacena información de campo para dicho segundo bloque de control del citado bloque de control de cuadro.
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公开(公告)号：HK1069046A1
公开(公告)日：2005-05-06
申请号：HK05102297
申请日：2005-03-15
Applicant: IBM
Inventor： ALLEN JAMES JR , BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , GAUR SANTOSH PRASAD , HEDDES MARCO C , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
IPC: G06F15/16 , G06F15/177 , H04L20060101 , H04J20060101 , H04L12/56 , H04Q20060101 , H04Q3/00 , H04Q3/545
Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
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公开(公告)号：PL355786A1
公开(公告)日：2004-05-17
申请号：PL35578600
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVID GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：HK1054098A1
公开(公告)日：2003-11-14
申请号：HK03106314
申请日：2003-09-05
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , MARCO HEDDES , KENNETH JENKINS STEVEN , BOYD LEAVENS ROSS , STEVEN SIEGEL MICHAEL , JEAN VERPLANKEN FABRICE
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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