公开(公告)号：JP2007243176A

公开(公告)日：2007-09-20

申请号：JP2007039055

申请日：2007-02-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TONTI WILLIAM R ,  MANDELMAN JACK A ,  HSU LOUIS LU-CHEN ,  WILLIAM P HOVIS ,  YANG CHIH-CHAO

IPC: H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an electrically programmable fuse structure for IC, and its manufacturing method. SOLUTION: This electrically programmable fuse has a first terminal part and second terminal part that are interconnected with fuse and elements. The first terminal part and second terminal part exist in different heights to the support surface of the fuse structure. The interconnecting fuse element connects the height difference between the height of the first terminal part and the second terminal part. While the first terminal part and second terminal part are oriented to be parallel with the support surface, the fuse element include a part oriented to be a right angle to the support surface, and also include at least one right-angled curvature portion that connects at least one of the first terminal element and second terminal element and the part of the fuse element oriented to be right angle. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为IC提供电可编程熔丝结构及其制造方法。 解决方案：该电可编程熔丝具有与熔丝和元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分与熔丝结构的支撑表面存在不同的高度。 互连保险丝元件连接第一端子部分和第二端子部分的高度之间的高度差。 当第一端子部分和第二端子部分被取向为与支撑表面平行时，熔丝元件包括定向成与支撑表面成直角的部分，并且还包括至少一个直角曲率部分，其连接在 第一端子元件和第二端子元件中的至少一个和熔丝元件的一部分被定向为直角。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2008045989A3

公开(公告)日：2008-09-12

申请号：PCT/US2007081046

申请日：2007-10-11

Applicant: IBM ,  YANG CHIH-CHAO ,  YANG HAINING S ,  WONG KEITH KWONG HON ,  FAROOQ MUKTA G

Inventor： YANG CHIH-CHAO ,  YANG HAINING S ,  WONG KEITH KWONG HON ,  FAROOQ MUKTA G

IPC: H01L21/469

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the interface of the capping layer (61), the underlying dielectric layer (12) and the diffusion barrier (31). The interconnect structure has a portion (41) of the diffusion barrier material (31) embedded in the capping material (61). The barrier (31) can be either partially or fully embedded in the capping layer (61).

Abstract translation: 本发明提供一种半导体互连结构，其在封盖层（61），下面的介电层（12）和扩散阻挡层（31）的界面处具有改进的机械强度。 互连结构具有嵌入封盖材料（61）中的扩散阻挡材料（31）的一部分（41）。 阻挡层（31）可以部分地或完全嵌入封盖层（61）中。

公开(公告)号：WO2007016047A3

公开(公告)日：2008-01-03

申请号：PCT/US2006028718

申请日：2006-07-24

Applicant: IBM ,  GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

Inventor： GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: B82Y10/00 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

Abstract translation: 磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。 上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

公开(公告)号：WO2013095692A3

公开(公告)日：2013-10-24

申请号：PCT/US2012032040

申请日：2012-04-04

Applicant: IBM ,  YANG CHIH-CHAO ,  GATES STEPHEN M ,  LI BAOZHEN ,  EDELSTEIN DAN

Inventor： YANG CHIH-CHAO ,  GATES STEPHEN M ,  LI BAOZHEN ,  EDELSTEIN DAN

IPC: H01L21/82 ,  H01L21/8242 ,  H01L23/62 ,  H01L27/108

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved electrical-fuse (e-fuse) device (200) including a dielectric layer (102) having a first top surface (108), two conductive features (104, 106) embedded in the dielectric layer (102) and a fuse element (122). Each conductive feature (104, 106) has a second top surface (110, 112) and a metal cap (114, 116) directly on the second top surface (110, 112). Each metal cap (114, 116) has a third top surface (118, 120) that is above the first top surface (108) of the dielectric layer (102). The fuse element (122) is on the third top surface (118, 120) of each metal cap (114, 116) and on the first top surface (108) of the dielectric layer (102). A method of forming the e-fuse device (200) is also provided.

Abstract translation: 一种改进的电熔丝（e熔丝）装置（200），包括具有第一顶表面（108）的介电层（102），嵌在电介质层（102）中的两个导电特征（104,106）和熔丝元件 （122）。 每个导电特征（104,106）具有直接在第二顶表面（110,112）上的第二顶表面（110,112）和金属盖（114,116）。 每个金属帽（114,116）具有在介电层（102）的第一顶表面（108）上方的第三顶表面（118,120）。 熔丝元件（122）位于每个金属盖（114,116）的第三顶表面（118,120）上并且位于介电层（102）的第一顶表面（108）上。 还提供了形成电熔丝装置（200）的方法。

公开(公告)号：WO2011037710A2

公开(公告)日：2011-03-31

申请号：PCT/US2010046267

申请日：2010-08-23

Applicant: IBM ,  HSU LOUIS L ,  OUYANG XU ,  YANG CHIH-CHAO

Inventor： HSU LOUIS L ,  OUYANG XU ,  YANG CHIH-CHAO

IPC: G11C11/24 ,  G11C11/34

CPC classification number: H01L28/40 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T307/865 ,  H01L2924/00

Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Abstract translation: 模块化电容器阵列包括多个电容器模块。 每个电容器模块包括电容器和被配置为电连接电容器的开关装置。 开关装置包括感测单元，该感测单元被配置为检测电容器的泄漏水平，使得如果泄漏电流超过预定水平，则开关装置电切断电容器。 每个电容器模块可以包括单个电容器板，两个电容器板或两个以上的电容器板。 采用泄漏传感器和开关装置来电切断电容器阵列中任何变得泄漏的电容器模块，由此保护电容器阵列免于过度的漏电。

公开(公告)号：WO2008051674A3

公开(公告)日：2008-08-28

申请号：PCT/US2007079375

申请日：2007-09-25

Applicant: IBM ,  YANG CHIH-CHAO ,  YANG HAINING

Inventor： YANG CHIH-CHAO ,  YANG HAINING

IPC: G11C17/14

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a trench feature in a substrate, depositing fuse material in the trench feature and compressive stress liner material over the fuse material, and patterning the compressive stress liner material.

Abstract translation: 半导体熔丝包括熔丝元件和减小熔丝元件的电迁移电阻的压应力衬垫。 该方法包括在衬底中形成沟槽特征，在沟槽特征中沉积熔丝材料并将压应力衬垫材料沉积在熔丝材料上，以及对压应力衬垫材料进行图案化。

公开(公告)号：WO2012170142A3

公开(公告)日：2013-05-16

申请号：PCT/US2012037212

申请日：2012-05-10

Applicant: IBM ,  YANG CHIH-CHAO ,  COHEN STEPHAN A ,  BAOZHEN LI

Inventor： YANG CHIH-CHAO ,  COHEN STEPHAN A ,  BAOZHEN LI

IPC: H01L29/00 ,  H01L21/205 ,  H01L21/8238

CPC classification number: B82Y10/00 ,  H01L23/5252 ,  H01L29/413 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A switching device (140 or 240) including a first dielectric layer (102 or 207) having a first top surface (108 or 218), two conductive features (104, 106 or 214, 216) embedded in the first dielectric layer (102 or 207), each conductive feature (104, 106 or 214, 216) having a second top surface (110, 112 or 220, 222) that is substantially coplanar with the first top surface (108 or 218) of the first dielectric layer (102 or 207), and a set of discrete islands of a low diffusion mobility metal (114a-c or 204a-c) between the two conductive features (104, 106 or 214, 216). The discrete islands of the low diffusion mobility metal (114a-c or 204a-c) may be either on the first top surface (108) or embedded in the first dielectric layer (207). The electric conductivity across the two conductive features (104, 106 or 214, 216) of the switching device (140 or 240) increases when a prescribed voltage is applied to the two conductive features (104, 106 or 214, 216). A method of forming such a switching device (140 or 240) is also provided.

Abstract translation: 一种包括具有第一顶表面（108或218）的第一介电层（102或207），嵌入第一介电层（102或210）中的两个导电特征（104,106或214,216）的开关装置（140或240） 每个导电特征（104,106或214,216）具有与第一介电层（102）的第一顶表面（108或218）基本上共面的第二顶表面（110,112或220,222） 或207），以及一组在两个导电特征（104,106或214,216）之间的低扩散迁移率金属（114a-c或204a-c）的离散岛。 低扩散迁移率金属（114a-c或204a-c）的离散岛可以在第一顶表面（108）上或嵌入在第一介电层（207）中。 当规定的电压施加到两个导电特征（104,106或214,216）时，开关装置（140或240）的两个导电特征（104,106或214,216）的电导率增加。 还提供了一种形成这种开关装置（140或240）的方法。

公开(公告)号：WO2011139417A3

公开(公告)日：2012-01-05

申请号：PCT/US2011029127

申请日：2011-03-21

Applicant: IBM ,  HORAK DAVID V ,  NOGAMI TAKESHI ,  PONOTH SHOM ,  YANG CHIH-CHAO

Inventor： HORAK DAVID V ,  NOGAMI TAKESHI ,  PONOTH SHOM ,  YANG CHIH-CHAO

IPC: H01L23/48

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.

Abstract translation: 提供具有自对准电介质盖的互连结构。 在基板上形成至少一个金属化层。 电介质盖被选择性地沉积在金属化层上。

公开(公告)号：WO2007127503A8

公开(公告)日：2008-09-04

申请号：PCT/US2007060564

申请日：2007-01-16

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL ,  WONG KWONG-HON ,  YANG CHIH-CHAO

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L27/1203 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/84 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Abstract translation: 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在衬底上的第二栅电极; 以及包括与第二栅电极重叠的一对凸缘端的着陆焊盘，其中第二栅电极的结构与着陆焊盘的结构不连续。

公开(公告)号：WO2008069832A2

公开(公告)日：2008-06-12

申请号：PCT/US2007011437

申请日：2007-05-11

Applicant: IBM ,  YANG CHIH-CHAO ,  VAN DER STRATEN OSCAR

Inventor： YANG CHIH-CHAO ,  VAN DER STRATEN OSCAR

IPC: H01L23/52

CPC classification number: H01L21/76834 ,  H01L21/288 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76852 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer.

Abstract translation: 提供了可靠和机械强的互连结构，其不包括开口底部的特别是在通孔底部的气泡特征。 相反，本发明的互连结构利用选择性地沉积在位于较低互连级别的导电特征的暴露表面上的含Co缓冲层。 选择性沉积通过存在于上部互连电平的电介质材料中的至少一个开口进行。 选择性沉积通过电镀或无电镀进行。 含Co缓冲层包含Co和P和B中的至少一个.W可选地也可存在于含Co缓冲层中。