公开(公告)号：EP1875499A4

公开(公告)日：2009-11-04

申请号：EP06749449

申请日：2006-04-07

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C

IPC: H01L21/8242 ,  H01L21/20

CPC classification number: H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1911096A4

公开(公告)日：2008-10-22

申请号：EP06788341

申请日：2006-07-24

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO ,  GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A

IPC: H01L27/22 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/528 ,  H01L43/12

CPC classification number: B82Y10/00 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

公开(公告)号：EP1461828A4

公开(公告)日：2005-09-28

申请号：EP02803310

申请日：2002-11-07

Applicant: IBM

Inventor： VOLANT RICHARD P ,  BISSON JOHN C ,  COTE DONNA R ,  DALTON TIMOTHY J ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: B81B3/00 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00

CPC classification number: B81C1/00246 ,  B81B2201/016 ,  B81B2201/018 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0122 ,  B81C2203/0735 ,  H01G5/40 ,  H01H59/0009

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

公开(公告)号：EP2250123A4

公开(公告)日：2014-10-15

申请号：EP09709244

申请日：2009-02-03

Applicant: IBM

Inventor： BLACK CHARLES T ,  DALTON TIMOTHY J ,  DORIS BRUCE B ,  RADENS CARL

IPC: B82B3/00 ,  B81C1/00

CPC classification number: H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

公开(公告)号：EP1994563A4

公开(公告)日：2011-06-22

申请号：EP07797080

申请日：2007-01-16

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL ,  WONG KWONG-HON ,  YANG CHIH-CHAO

IPC: H01L27/01 ,  H01L21/8234

CPC classification number: H01L27/1203 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/84 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2140458A4

公开(公告)日：2010-05-05

申请号：EP07867608

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  DEBROSSE JOHN K ,  HSU LOUIS L C ,  RADENS CARL ,  WONG KEITH K H ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

CPC classification number: G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

公开(公告)号：JP2004200684A

公开(公告)日：2004-07-15

申请号：JP2003413888

申请日：2003-12-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN SHYNG-TSONG ,  DALTON TIMOTHY J ,  DAVIS KENNETH M ,  HU CHAO-KUN ,  JAMIN FEN F ,  KALDOR STEFFEN K ,  KRISHNAN MAHADEVAIYER ,  KUMAR KAUSHIK ,  MICHAEL F ROFARO ,  SANDRA G MARUHOTORA

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide the structure of an integrated circuit having a logic/functional device layer and an interconnection layer above it. SOLUTION: This interconnection layer has a substrate, a conductive feature 122 in the substrate, and a cap 151 which is formed only above the conductive feature. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004080017A

公开(公告)日：2004-03-11

申请号：JP2003275624

申请日：2003-07-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GATES STEPHEN M ,  DALTON TIMOTHY J ,  PHIZHIMONS JOHN A

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/53295 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a novel interconnecting structure possessing relatively low internal stress and a dielectric constant for use in semiconductor devices. SOLUTION: This structure is provided with at least one of each of a first interconnecting level 9 provided with a first layer 10, a second interconnecting level 28 provided with a second layer 30, and a stress adjustment cap layer 22 that is formed between the first layer 10 and the second layer 30. The first interconnecting level 9 is stacked. Each has a coefficient of thermal expansion greater than about 20ppm, and is provided with the first layer 10 having the first internal stress. The first layer 10 is provided with a first set of metal wires 14 that are formed in it. The second interconnecting level 28 is stacked. Each has a coefficient of thermal expansion less than about 20ppm, and is provided with the second layer 30 having the second internal stress. The second layer 30 is provided with a second set of metal wires 34 that are formed in it. The stress adjustment cap layer 22 is selected to offset the first internal stress of the first layer 10 and the second internal stress of the second layer 30. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003218109A

公开(公告)日：2003-07-31

申请号：JP2003003569

申请日：2003-01-09

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  ANAND MINAKSHISUNDARAN B ,  ARMACOST MICHAEL D ,  CHEN SHYNG-TSONG ,  GATES STEPHEN M ,  GRECO STEPHEN E ,  KARECKI SIMON M ,  NITTA SATYANARAYANA V

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a metallic pattern on a low-dielectric constant substrate. SOLUTION: A hard mask including a lower hard mask layer 31 and an upper hard mask layer 20 is prepared. The upper hard mask layer 20 is a sacrifice layer of about 200 Å thick, which is preferably made of high-melting-point nitride. The sacrifice layer functions as a stop layer in the following CMP metal removal process. A resist layer is used to perform patterning. A protection layer 31t is formed on a hard mask, or a non-oxidized resist strip process is used, so as to avoid the damage of oxidization to the lower hard mask layer 31. COPYRIGHT: (C)2003,JPO

公开(公告)号：EP1920493A4

公开(公告)日：2011-05-04

申请号：EP06802645

申请日：2006-08-30

Applicant: IBM

Inventor： HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01H50/00 ,  H01P1/10

CPC classification number: H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147