Abstract:
PROBLEM TO BE SOLVED: To provide fault tolerant design applicable to memory in any size by using redundant replacement configuration in variable size for selectively replacing a fault element with the redundant element in the same size. SOLUTION: The variable redundant array replacement configuration is provided with plural redundant units(RU) having variable number of redundant elements(RE) for each RU and at any RU, all the RE are simultaneously replaced by prescribed repair. For example, RU0-7 , RU8-11 , RU12-13 , RU14 and RU15 respectively have 1, 2, 4, 8 and 32 pieces of RE. At all the RU0-7 , single fault is repaired and at all the RU8-11 , the fault caused by short-circuiting generated between defective bit lines or elements is repaired. Then, the R12-13 , R14 and RU15 are secured for processing the much severe fault at a fault decoder or the like. Then, the RU is controlled by respectively correspondent redundant unit control circuit (RUCNT).
Abstract:
Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first gate. The first source/drain area is coupled to the second end of the eFuse, the second source/drain area is coupled to ground, and the first gate is coupled to a first node. The eFuse cell includes a senseFET having a third source/drain area, a fourth source/drain area, and a second gate. The second gate is coupled to the first node, and the third source/drain area is coupled to a second node. The second node is coupled to an operation signal and the second end of the eFuse. The eFuse cell includes a select eFuse logic element having an input to receive a select eFuse signal and an output coupled to the first node.
Abstract:
A dynamic random access memory (DRAM) storage device includes a storage cell having a plurality of transistors arranged in a gain cell configuration, the gain cell coupled to a read bitline and a write bitline. A dummy cell is configured as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of the storage cell.
Abstract:
There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups (102); at least one sense amplifier (SA); a first and a second multiplexer (MUXs); and at least one programmable control device (control circuit). Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.
Abstract:
A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.
Abstract:
PROBLEM TO BE SOLVED: To provide a concurrent refresh mode using distributed row address counter in a buried dynamic random access memory. SOLUTION: A concurrent refresh mode is realized by refreshing the memory array by refresh bank selection signals while enabling concurrent memory access in another array. The refresh address management is simplified sharply by inserting a row address counter incorporated in each array. In a desirable embodiment of this invention, an arbitrary combination of two or more memory arrays is refreshed concurrently while enabling memory access. This concurrent mode also supports a multibank operation. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a memory architecture, in which coupling noise between bit lines is small at CMOS intersection coupling sensing operation, and which operates at a high speed. SOLUTION: In a single bit-line direct sensing architecture, a sense amplifier circuit, having four transistors arranged for each memory array, is used. In this circuit, the transistor functions so that a data bit from a true bit-line of a pair of bit line or an auxiliary bit line is transferred selective to a data line. The data line is preferably arranged on a plurality of memory arrays, and the data line may not be required, to share in read operation and write operation. Furthermore, digital sensing scheme function is performed, by charging a data line during read-out operation using one more current source detecting the ratio of a current source, driving by a bit line of a corresponding array and resistance of a transistor. COPYRIGHT: (C)2003,JPO
Abstract:
PROBLEM TO BE SOLVED: To provide a memory device including a means coupling plural data storing cells, at least one redundant data storing cell, a redundant match detecting circuit, and a programmable fuse to a redundant match detecting circuit. SOLUTION: When a redundant match detecting circuit detects the prescribed condition set by a programmable fuse, a defective data is replaced by one redundant data storage region. Decoding is achieved by selecting an (e) fuse to be cut off by a data bus. Data bus, also, reads a state of the (e) fuse, and is used for guaranteeing that the (e) fuse is correctly cut off. Electric power is applied effectively to a selected (e) fuse while the data bus is shared to decode and verify the (e) fuse. Time-muliplex is used for transfer operation to reduce the number of communication channels between the (e) fuse and the redundant match detecting circuit, and transferring successively (e) fuse information to the redundant match detecting circuit can be performed. Actual time-multiplex operation for performing transfer is preferable to make 'enable' only after a chip is made a power source apply state.
Abstract:
PROBLEM TO BE SOLVED: To provide a selectable function which makes the address portion of data words separable and enables the address portion to be used for a different purpose without disturbing the contents stored in a memory array. SOLUTION: A memory assembly which has an input port 242, an output port 216, and the memory array 23 containing a plurality of addressable storing positions in one mode contains the selectable function which sends the address information portion 212 of data which appear in a data route to other processing routes 770 and 771 by by-passing the memory array 232 without disturbing the information stored at the addressable storing positions.
Abstract:
PROBLEM TO BE SOLVED: To array a larger number of fuses densely by electrically connecting at least two fuses that contain a fusing part arrayed in a first level of a multi- layer semiconductor device, respectively. SOLUTION: Each fuse 13 contains a part 15 that is actually fused. The part 15 to be fused is arrayed in a first metal level M1. Like the other part of the fuse 13, the part 15 that is actually fused is made typically of a electrically conductive material, especially aluminum. A termination of each part 15 to be fused is connected to a connector bias 17 that connects that fuse 13 with a connector 19. A gate contact 23 is vertical to a direction of the fuse 13. The gate contact 23 can be connected to a ground that is common to all of existing fuse circuits. Therefore, fuse density is doubled without narrowing the fuse pitch.