公开(公告)号：JP2002026148A

公开(公告)日：2002-01-25

申请号：JP2001189096

申请日：2001-06-22

Applicant: IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  GRUENING ULRIKE ,  SUDO AKIRA

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a new deep trench(DT) collar process which reduces disturbance of strap diffusion to an array metal oxide semiconductor field effect transistor(MOSFET) of a semiconductor device. SOLUTION: By this method, an oxidation barrier layer is formed on a sidewall of the DT provided in the semiconductor substrate, a photoresist layer of specific depth is provided in the trench to remove the oxidation barrier layer to specific depth and expose the trench sidewall, and the remaining photoresist is removed. A layer of a silicon material is stuck on the exposed trench sidewall, and a dielectric layer is formed on the silicon material layer to form a collar. The remaining oxidation barrier layer is removed from the trench and polysilicon which forms a storage node is charged. Consequently, the distance between a MOSFET gate and a DT storage capacitor is maximized, and the effective edge bias of the DT at its peak is reducible without spoiling the storage capacity.

公开(公告)号：JP2001223271A

公开(公告)日：2001-08-17

申请号：JP2001002760

申请日：2001-01-10

Applicant: IBM

Inventor： DIVAKARUNI RAMA ,  NESBIT LARRY A ,  RADENS CARL J

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To simultaneously form a line interconnection of a bit line or the like and borderless contact to a diffused part such as bit line contact. SOLUTION: A semiconductor substrate contains a previously patterned gate stack 12 on the substrate, is covered with a first dielectric substance 40 for forming a first level 42 and then deposited with a second dielectric substance 44 to form a second level 46. A line interconnection opening 62 is formed at a second level 46 by a lithography and etching. The etching is continued to a microcrystallized region of an array region 30 of the substrate, and formed with a borderless contact opening between the gate stacks 12 corresponding to the line interconnection such as an opening of the bit line or the like. These openings are filled with one or more conductors to form the contact with the diffused part such as bit line contact or the like corresponding to the line interconnection of the bit line or the like.

公开(公告)号：JP2000353795A

公开(公告)日：2000-12-19

申请号：JP2000139018

申请日：2000-05-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/60 ,  H01L21/8242 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To obtain a method of manufacturing an LSI which contains a vertical transistor and is lessened in size, provided at a low cost, and enhanced in reliability. SOLUTION: A capacitor 41 composed of a trench 13, an insulating film 14, and a conductor 16 is formed in a substrate 10, and a stepped part is provided at the upper part of an opening 50 bored in the substrate 10, and then the opening 50 is filled with insulator for the formation of an isolation region 50. The upper part of the stepped part is filled with a conductive material to serve as a strap 904, and N-type ions are implanted for the formation of a source region 61 inside the substrate 10. An insulating film 905 is attached, a gate electrode 108 is deposited, a trench 105 is cut by etching, a spacer 103 is attached, then N-type ions are implanted to form a drain region 106 adjacent to the upper gate 108, and the opening 105 is filled up with conductor to serve as a contact. The strap 904 serves as a source electrode which crosses the capacitor 41 at grade and is electrically connected to the contact 105, which serves as a drain electrode through the intermediary of diffusion regions 61 and 106 located inside the substrate 10.

公开(公告)号：JP2000164697A

公开(公告)日：2000-06-16

申请号：JP33676599

申请日：1999-11-26

Applicant: IBM ,  SIEMENS AG

Inventor： GARY B BRONER ,  COSTRINI GREG ,  RADENS CARL J ,  RAYNER E SCHNABEL

IPC: H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To achieve low capacitance and low resistance by simultaneously performing the pattern formation of a via and a grooved line in an interlayer dielectric, by simultaneously etching the via and the grooved line, and by simultaneously filling the via and the grooved line with metal. SOLUTION: On a substrate, desired linear features and vertical interconnection are formed (S700). A grooved line and a via are simultaneously etched (S701). A metallization layer is subjected pattern formation by lithography, and is etched by RIE or the like (S702). The via and the grooved line are filled by the same metallization process (S703). The filled via and the grooved line are finished by one-time common etching or polishing process so that a structure has a flat and uniform upper surface (S704). As a result, both of low-capacitance and low-resistance metallization can be formed.

公开(公告)号：JP2000058779A

公开(公告)日：2000-02-25

申请号：JP21476499

申请日：1999-07-29

Applicant: IBM ,  SIEMENS AG

Inventor： BRONNER GARY B ,  ECONOMIKOS LAERTIS ,  JAMMY RAJARAO ,  PARK BYEONGJU ,  RADENS CARL J ,  SCHREMS MARTIN E

IPC: H01L21/02 ,  H01L21/3215 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a trench capacitor structure suited for use in a semiconductor integrated circuit device and also provide a process sequence used for forming the structure. SOLUTION: A trench structure wherein a trench is demarcated in a semiconductor substrate 100 includes a trench wall, a silicon buried plate 14 doped with conductive species existing in part of the semiconductor substrate around the trench wall, and a silicon structure with texture formed along part of the trench wall. This trench capacitor has improved capacitance by including a capacitor plate constituted of semispherical silicons with texture.

公开(公告)号：JPH11260935A

公开(公告)日：1999-09-24

申请号：JP4799

申请日：1999-01-04

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a cap self-aligned on a gate conductor, and realize a two actional function for selectively applying P doping and N doping to the gate conductor. SOLUTION: A selected number of gate structures having self-aligned insulating layers 2 and 4 are doped by a first conductive type dopant through at least one sidewall of the gate structure. Thus, one gate structure is doped with the first conductive dopant, and another gate structure is doped with a second and different conductive dopant in this gate structural array. Therefore, a two actional function can be given.

公开(公告)号：DE69939451D1

公开(公告)日：2008-10-16

申请号：DE69939451

申请日：1999-10-15

Applicant: IBM

Inventor： RADENS CARL J ,  WEYBRIGHT MARY E

IPC: H01L27/108 ,  H01L21/8242

Abstract: A memory cell structure uses field-effect controlled majority carrier depletion of a buried strap region for controlling the access to a trench-cell capacitor. The buried strap connection between the trench capacitor and the bitline contact (CB) in regions where the deep trench pattern intersects the active area of the device. The upper section of the trench contains a single crystalline material to minimize the amount of leakage. The memory cell structure includes a field-effect switch having a gate terminal which induces the depletion region in the substrate and the top of the trench, the extent of the depletion region varying as a function of a voltage applied to the gate terminal; a storage device that includes an isolation collar (400) and a capacitor, the depletion region overlapping the isolation collar when the field-effect switch is in an off- state, and the depletion region does not overlap the isolation collar when the field effect switch is in an on-state.

公开(公告)号：HK1042377A1

公开(公告)日：2002-08-09

申请号：HK02102046

申请日：2002-03-18

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  RADENS CARL J

IPC: H01L20060101 ,  H01L

公开(公告)号：DE69934357D1

公开(公告)日：2007-01-25

申请号：DE69934357

申请日：1999-06-17

Applicant: SIEMENS AG ,  IBM

Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L21/8242 ,  H01L27/108

Abstract: Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

公开(公告)号：DE10220542A1

公开(公告)日：2002-12-05

申请号：DE10220542

申请日：2002-05-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： RADENS CARL J ,  MANDELMAN JACK A ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/94

Abstract: A semiconductor device includes at least two active areas, each active area surrounding a corresponding trench in a substrate. The trenches each include a capacitor in a lower portion of the trench and a gate in an upper portion of the trench. A vertical transistor is formed adjacent to the trench in the upper portion for charging and discharging the capacitor. A body contact is formed between the at least two active areas. The body contact connects to the at least two active areas and to a diffusion well of the substrate for preventing floating body effects in the vertical transistor.