公开(公告)号：HK1012743A1

公开(公告)日：1999-08-06

申请号：HK98113950

申请日：1998-12-17

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  SA REYNOLD V D

IPC: G06F9/38 ,  G06F

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：ZA979600B

公开(公告)日：1999-04-28

申请号：ZA979600

申请日：1997-10-27

Applicant: INTEL CORP

Inventor： SAGER DAVID J ,  FLETCHER THOMAS D ,  HINTON GLENN J ,  UPTON MICHAEL D

IPC: G06F1/08 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F

Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

公开(公告)号：GB2285526B

公开(公告)日：1998-11-18

申请号：GB9425726

申请日：1994-12-20

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38 ,  G06F9/32

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：GB2287111B

公开(公告)日：1998-08-05

申请号：GB9500762

申请日：1995-01-16

Applicant: INTEL CORP

Inventor： HINTON GLENN J ,  PAPWORTH DAVID B ,  GLEW ANDREW F ,  FETTERMAN MICHAEL ALAN ,  COLWELL ROBERT P

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G09F13/04

Abstract: A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages. The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results. In one embodiment, the instructions are executed by determining the data readiness of each of the operations and scheduling data ready operations. These scheduled data ready operations are dispatched to an execution unit and executed. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages. The present invention also provides for retiring each of the continuous stream of operations in such a manner as to commit their results to architectural state and to reestablish sequential program order.

公开(公告)号：SG50456A1

公开(公告)日：1998-07-20

申请号：SG1996001862

申请日：1994-12-20

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38 ,  G06F9/32

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：SG49220A1

公开(公告)日：1998-05-18

申请号：SG1996007762

申请日：1994-04-22

Applicant: INTEL CORP

Inventor： ABRAMSON JEFFREY M ,  AKKARY HAITHAM ,  GLEW ANDREW F ,  HINTON GLENN J ,  KONIGSFELD KRIS G ,  MADLAND PAUL D

IPC: G06F9/28 ,  G06F9/38 ,  G06F15/16 ,  G06F15/177

公开(公告)号：SG47981A1

公开(公告)日：1998-04-17

申请号：SG1996005873

申请日：1995-01-16

Applicant: INTEL CORP

Inventor： HINTON GLENN J ,  PAPWORTH DAVID B ,  GLEW ANDREW F ,  FETTERMAN MICHAEL A ,  COLWELL ROBERT P

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G09F13/04 ,  G06F15/76 ,  G06F15/82

Abstract: A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages. The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results. In one embodiment, the instructions are executed by determining the data readiness of each of the operations and scheduling data ready operations. These scheduled data ready operations are dispatched to an execution unit and executed. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages. The present invention also provides for retiring each of the continuous stream of operations in such a manner as to commit their results to architectural state and to reestablish sequential program order.

公开(公告)号：DE4493224T1

公开(公告)日：1996-04-25

申请号：DE4493224

申请日：1994-04-08

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  GLEW ANDREW F ,  NATARAJAN SUBRAMANIAN

IPC: G06F9/38

公开(公告)号：ZA9504460B

公开(公告)日：1996-02-05

申请号：ZA9504460

申请日：1995-05-31

Applicant: INTEL CORP

Inventor： GLEW ANDREW F ,  HINTON GLENN J

IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08 ,  G06F

CPC classification number: G06F9/30043 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3857 ,  G06F12/0804 ,  G06F12/0888

公开(公告)号：GB2261087B

公开(公告)日：1996-01-03

申请号：GB9222512

申请日：1992-10-27

Applicant: INTEL CORP

Inventor： HINTON GLENN J ,  TIWARY GYANENDRA

IPC: G06F9/355 ,  G06F12/10

Abstract: A processor in which instructions and data at logical addresses are mapped onto real memory locations at physical addresses that are translated from the logical addresses by a translation lookaside buffer (TLB) that takes one clock phase to perform this function. The TLB only needs the upper 20 bits of a logical address, which bits correspond to the logical page number, to do the translation to a physical address. The lower 12 bits are not needed until the TLB translation is done. The add of the "base-plus-displacement/offset" usually does not cross a page boundary, that is, the upper 20 bits are the same after the add. A mechanism takes this into account and guesses that the upper 20 bits will not change, and sends them to the TLB. In parallel with the TLB translation, the effective address add of the "base-plus-displacement" is computed. After the add, if the upper 20 bits did not change, then the 20 physical address bits from the TLB plus the lower 12 bits from the address computation are concatenated to produce the complete correct 32-bit physical address. If the upper 20 bits did change due to the actual add then the logical page number (the upper 20 bits) that were given the TLB were wrong. This is detected and a signal is generated that tells the memory side to redo the last memory access, and to use the new 32-bit logical address that was just computed by the effective address-generation hardware.