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    Processor having execution core sections operating at different clock rates
    3.
    发明专利
    Processor having execution core sections operating at different clock rates 未知

    公开(公告)号：ZA979600B

    公开(公告)日：1999-04-28

    申请号：ZA979600

    申请日：1997-10-27

    Applicant: INTEL CORP

    Inventor： SAGER DAVID J ,  FLETCHER THOMAS D ,  HINTON GLENN J ,  UPTON MICHAEL D

    IPC: G06F1/08 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F

    Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

    Reduzierung des Leistungsverbrauchs in einer fusionierten Multiplizier-Addier-(FMA)-Einheit in Reaktion auf Eingangsdatenwerte
    4.
    发明专利
    Reduzierung des Leistungsverbrauchs in einer fusionierten Multiplizier-Addier-(FMA)-Einheit in Reaktion auf Eingangsdatenwerte 未知

    公开(公告)号：DE102013111605A1

    公开(公告)日：2014-04-30

    申请号：DE102013111605

    申请日：2013-10-22

    Applicant: INTEL CORP

    Inventor： HICKMANN BRAIN J ,  BRADFORD DENNIS R ,  FLETCHER THOMAS D

    IPC: G06F7/38

    Abstract: In einer Ausführungsform ist eine fusionierte Multiplizier-Addier-(FMA)-Schaltung konfiguriert, um eine Mehrzahl von Eingangsdatenwerten zu empfangen, um einen FMA-Befehl auf die Eingangsdatenwerte auszuführen. Die Schaltung umfasst eine Multiplizier-Einheit und eine Addier-Einheit, die mit einem Ausgang der Multiplizier-Einheit gekoppelt ist, und eine Steuerungslogik, um die Eingangsdatenwerte zu empfangen, und um eine Schaltaktivität zu reduzieren und somit den Stromverbrauch eines oder mehrerer Komponenten der Schaltung basierend auf einem Wert eines oder mehrerer der Eingangsdatenwerte zu reduzieren. Andere Ausführungsformen werden beschrieben und beansprucht.

    Processor having sections operating at different rates
    6.
    发明专利
    Processor having sections operating at different rates 未知

    公开(公告)号：AU4669297A

    公开(公告)日：1998-06-03

    申请号：AU4669297

    申请日：1997-10-02

    Applicant: INTEL CORP

    Inventor： SAGER DAVID J ,  FLETCHER THOMAS D ,  HINTON GLENN J ,  UPTON MICHAEL D

    IPC: G06F1/08 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F1/32

    Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

    High gain pulse generator circuit for clocking
    9.
    发明专利
    High gain pulse generator circuit for clocking 未知

    公开(公告)号：AU1999299A

    公开(公告)日：1999-07-19

    申请号：AU1999299

    申请日：1998-12-16

    Applicant: INTEL CORP

    Inventor： MILSHTEIN MARK S ,  FLETCHER THOMAS D ,  CHAPPELL TERRY I

    IPC: H03K5/00 ,  H03K5/13 ,  H03K5/156 ,  H03K3/00

    Abstract: A pulse generating circuit includes a first pulse generating circuit for generating a first output pulse, and a second pulse generating circuit for outputting a second output pulse. Each pulse generating circuit comprises a stack of two n-channel transistors and a reset circuit. The reset circuit includes two p-channel transistors and two inverters and is provided for automatically resetting the pulse generating circuits. The second pulse generating circuit includes a delay element for introducing an additional gate delay in the generation of the second output pulse. The additional gate delay introduces an asymmetry in the output pulses which offsets or cancels a previously introduced asymmetry of an input clock signal to generate an output clock signal having a constant period. Clock gating circuitry is provided for selectively enabling and disabling at least one of said pulse generator circuits.

    Reducing power consumption in a fused multiply-add unit responsive to input data values
    10.
    发明专利
    Reducing power consumption in a fused multiply-add unit responsive to input data values 未知

    公开(公告)号：GB2507656A

    公开(公告)日：2014-05-07

    申请号：GB201318169

    申请日：2013-10-14

    Applicant: INTEL CORP

    Inventor： HICKMANN BRIAN J ,  FLETCHER THOMAS D ,  BRADFORD DENNIS R

    IPC: G06F9/302 ,  G06F1/32 ,  G06F7/483 ,  G06F7/57

    Abstract: A processor and method comprises a fused multiply-add (FMA) circuit which includes a multiplier unit 110 and an adder unit 125 to compute a fused multiply add operation. If certain input data values are received at the FMA circuit, an exception occurs and components of the circuit will be clock gated to disable them and prevent them from toggling. If either of the two inputs to the multiplier unit are zero, then the multiplier and adder are gated and the addend provided as output 135. If one of the multiplier units is equal to one, then the multiplier is gated and the other multiplier input is directly provided to the adder. If the addend is zero, then the adder is gated and the product of the multiplier provided as output. If one of the multiplier inputs is equal to 2N, then the multiplier is gated and the other multiplier input directed to a left or right shifter 114. This processor might form part of multi-core processing system, and it is implemented to save power by bypassing the arithmetic units when they are not required.

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