公开(公告)号：US20170170111A1

公开(公告)日：2017-06-15

申请号：US14970355

申请日：2015-12-15

Applicant: Intel IP Corporation

Inventor： Klaus Jürgen REINGRUBER ,  Sven Albers ,  Christian Georg Geissler ,  Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/528 ,  H01L23/00 ,  H05K1/11 ,  C25D5/54 ,  C25D7/12 ,  C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  H01L23/522 ,  H05K1/02

CPC classification number: H01L23/528 ,  C25D5/022 ,  C25D5/10 ,  C25D5/48 ,  C25D5/54 ,  C25D7/123 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115

Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

公开(公告)号：US20210273342A1

公开(公告)日：2021-09-02

申请号：US17323278

申请日：2021-05-18

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC: H01Q19/06 ,  H01Q15/08 ,  H01L23/66 ,  H01L23/528 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/13 ,  H01Q1/48

Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

公开(公告)号：US20200286982A1

公开(公告)日：2020-09-10

申请号：US16881954

申请日：2020-05-22

Applicant: Intel IP Corporation

Inventor： Veronica Sciriha ,  Georg Seidemann

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/00 ,  H01L23/64

Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.

公开(公告)号：US20200227388A1

公开(公告)日：2020-07-16

申请号：US16641241

申请日：2017-09-29

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin ,  Sonja Koller ,  Thomas Ort ,  Reinhard Mahnkopf

IPC: H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

公开(公告)号：US20200185490A1

公开(公告)日：2020-06-11

申请号：US16617548

申请日：2017-06-30

Applicant: INTEL IP CORPORATION

Inventor： Georg Seidemann ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Andreas WOLTER ,  Andreas AUGUSTIN

IPC: H01L49/02 ,  H01L23/64 ,  H01L23/00 ,  H01L21/02 ,  H01L21/56 ,  H01F17/04

Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.

公开(公告)号：US10672731B2

公开(公告)日：2020-06-02

申请号：US15776051

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Richard Patten

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US10658201B2

公开(公告)日：2020-05-19

申请号：US15935128

申请日：2018-03-26

Applicant: Intel IP Corporation

Inventor： Sonja Koller ,  Georg Seidemann ,  Bernd Waidhas

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498

Abstract: A method for forming a carrier substrate for a semiconductor device, the method includes providing a substrate layer including conductive particles embedded in an electrically insulating material and localized heating of the substrate layer along a desired trace by a laser to form a conductive trace of merged particles along the desired trace.

公开(公告)号：US20200068711A1

公开(公告)日：2020-02-27

申请号：US16343961

申请日：2016-11-23

Applicant: Intel IP Corporation

Inventor： Andreas Wolter ,  Georg Seidemann ,  Klaus Reingruber ,  Thomas Wagner

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/00 ,  H05K3/34

Abstract: Systems and methods are provide to form one or more pads on at least one surface associated with a portion of a component, for example, a component associated with a surface-mounted device (SMD). Further, the systems and methods are directed to providing metal (for example, copper, Cu) layers on the surface of one or more terminations (for example, solder termination pads) of an electrical component. In one embodiment, the metal layers include metal termination pads that are fabricated on a carrier layer; components can be soldered to these termination pads, then the components with the metal pads can be debonded from the carrier layer. As such, the solder terminations of the components can be covered by the metal pads.The disclosed systems and methods can permit or otherwise facilitate a wider selection and easy availability of the components to be electrically and/or mechanically connected to semiconductor packages.

公开(公告)号：US10553538B2

公开(公告)日：2020-02-04

申请号：US16152221

申请日：2018-10-04

Applicant: Intel IP Corporation

Inventor： Klaus Jürgen Reingruber ,  Sven Albers ,  Christian Georg Geissler ,  Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/498 ,  H01L23/00 ,  C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  C25D5/54 ,  C25D7/12 ,  H01L23/522 ,  H05K1/02 ,  H05K1/11

Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

公开(公告)号：US10546826B2

公开(公告)日：2020-01-28

申请号：US16025575

申请日：2018-07-02

Applicant: Intel IP Corporation

Inventor： Georg Seidemann

IPC: H01L23/00 ,  H01L23/29 ,  H05K1/09

Abstract: A device and method of preventing corrosion of a copper layer in a PCB is disclosed. A first dielectric is disposed on a substrate. A copper layer is plated in an opening in the first dielectric and, after conditioning the copper layer, a redistribution layer is plated on the copper layer. A solder resist layer is disposed above the copper layer. A solder ball is disposed in an opening in the solder resist layer. The solder ball is in conductive contact with the copper layer and in physical contact with the redistribution layer. A non-conductive carbon layer is disposed on and in contact with the redistribution layer or tsi-diehe solder resist layer. The carbon layer is substantially thinner than the copper layer and acts as a diffusion barrier to moisture for the copper layer.