公开(公告)号：US11031699B2

公开(公告)日：2021-06-08

申请号：US15892632

申请日：2018-02-09

Applicant: Intel IP Corporation

Inventor： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC: H01Q19/06 ,  H01Q15/08 ,  H01L23/66 ,  H01L23/528 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/13 ,  H01Q1/48

Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

公开(公告)号：US11018114B2

公开(公告)日：2021-05-25

申请号：US16515979

申请日：2019-07-18

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/10 ,  H01L25/065 ,  H01L21/48 ,  H01L23/48 ,  H01L25/00 ,  H01L23/427 ,  G06F15/76

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US10700159B2

公开(公告)日：2020-06-30

申请号：US16020772

申请日：2018-06-27

Applicant: Intel IP Corporation

Inventor： Veronica Sciriha ,  Georg Seidemann

IPC: H01L23/64 ,  H01L49/02 ,  H01L23/522 ,  H01L23/00

Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.

公开(公告)号：US10403609B2

公开(公告)日：2019-09-03

申请号：US15776475

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Christian Geissler ,  Sven Albers ,  Georg Seidemann ,  Andreas Wolter ,  Klaus Reingruber ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/02 ,  H01L25/16 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.

公开(公告)号：US10366968B2

公开(公告)日：2019-07-30

申请号：US15282855

申请日：2016-09-30

Applicant: Intel IP Corporation

Inventor： Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

公开(公告)号：US20170284636A1

公开(公告)日：2017-10-05

申请号：US15087477

申请日：2016-03-31

Applicant: Intel IP Corporation

Inventor： Marc Stephan Dittes ,  Sven Albers ,  Christian Georg Geissler ,  Andreas Wolter ,  Klaus Reingruber ,  Georg Seidemann ,  Thomas Wagner ,  Richard Patten

IPC: F21V11/00 ,  F21V23/00 ,  H01L33/58 ,  H01L33/54 ,  H01L33/48 ,  H01L33/62

CPC classification number: H01L25/167 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2224/73257 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.

公开(公告)号：US09397019B2

公开(公告)日：2016-07-19

申请号：US14189938

申请日：2014-02-25

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及集成电路（IC）封装，其包括具有与第一侧相对设置的第一侧和第二侧的管芯。 IC封装还可以包括封装模具的至少一部分并且具有与模具的第一侧相邻的第一表面的封装材料和与第一表面相对设置的第二表面。 在实施例中，第二表面可以被成形为使得IC封装的一个或多个横截面积比IC封装的一个或多个其它横截面积更薄。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10727197B2

公开(公告)日：2020-07-28

申请号：US15464920

申请日：2017-03-21

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Thomas Wagner ,  Stephan Stoeckl ,  Laurent Millou

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683

Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.

公开(公告)号：US20200020629A1

公开(公告)日：2020-01-16

申请号：US16469113

申请日：2016-12-30

Applicant: Intel IP Corporation

Inventor： Thomas Wagner ,  Andreas Wolter ,  Georg Seidemann

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/538

Abstract: A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.

公开(公告)号：US20200006244A1

公开(公告)日：2020-01-02

申请号：US16020772

申请日：2018-06-27

Applicant: Intel IP Corporation

Inventor： Veronica Sciriha ,  Georg Seidemann

IPC: H01L23/552 ,  H01L49/02 ,  H01L23/522 ,  H01L23/00

Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.