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    COHERENCY TRACKING APPARATUS AND METHOD FOR AN ATTACHED COPROCESSOR OR ACCELERATOR
    41.
    发明申请
    COHERENCY TRACKING APPARATUS AND METHOD FOR AN ATTACHED COPROCESSOR OR ACCELERATOR 有权

    公开(公告)号：US20210200545A1

    公开(公告)日：2021-07-01

    申请号：US16728665

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Pratik Marolia ,  Rajesh Sankaran

    IPC: G06F9/30 ,  G06F9/38

    Abstract: An apparatus and method for hybrid software-hardware coherency. For example, one embodiment of an apparatus comprises: one or more processing elements to process data; a memory controller to couple the one or more processing elements to a device memory; an interconnect to couple the one or more processing elements to a host processor memory and to couple a host processor to the device memory; one or more device caches to store cache lines read from the host processor memory and/or the device memory; coherency circuitry to manage an ownership indication for each cache line, the ownership indication to be set to a first value to indicate ownership by the host processor and to be set to a second value to indicate ownership by the processing device, wherein the coherency circuitry is to transfer ownership of a first cache line from the processing device to the host processor by updating the ownership indication from the second value to the first value, the coherency circuitry to provide indirect access to the cache line by the processing device while the ownership indication is set to the first value, the coherency circuitry to maintain the ownership indication at the first value until receiving a request to change the ownership indication.

    Updating persistent data in persistent memory-based storage
    42.
    发明授权
    Updating persistent data in persistent memory-based storage 有权
    在永久存储器存储中更新持久数据

    公开(公告)号：US09430396B2

    公开(公告)日：2016-08-30

    申请号：US14579934

    申请日：2014-12-22

    Applicant: Intel Corporation

    Inventor： Sanjay Kumar ,  Rajesh Sankaran ,  Subramanya Dulloor ,  Sheng Li

    IPC: G06F12/08 ,  G06F3/06

    CPC classification number: G06F12/128 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F3/0671 ,  G06F11/00 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1027 ,  G06F2212/1032 ,  G06F2212/6028 ,  G06F2212/621

    Abstract: A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache that includes a cache line associated with the transaction, the cache line being associated with a cache line status, and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to, in response to determining that the cache line status that the cache line is committed, evict contents of the cache line to the persistent memory, and in response to determining that the cache line status indicating that the cache line is uncommitted, discard the contents of the cache line.

    Abstract translation: 处理器包括处理核心，用于执行包括通过包括与事务相关联的高速缓存行的易失性高速缓冲存储器与持久存储器进行交易的指令的应用，所述高速缓存行与高速缓存行状态相关联，高速缓存控制器可操作地耦合 响应于确定高速缓存行被提交的高速缓存行状态，缓存控制器响应于检测到故障事件，将高速缓存行的内容驱逐到永久存储器，并且响应于缓存行 确定指示高速缓存行未被提交的高速缓存行状态，丢弃高速缓存行的内容。

    High-performance input-output devices supporting scalable virtualization
    45.
    发明授权
    High-performance input-output devices supporting scalable virtualization 有权

    公开(公告)号：US12164971B2

    公开(公告)日：2024-12-10

    申请号：US18301733

    申请日：2023-04-17

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Sanjay Kumar ,  Kun Tian ,  Philip Lantz

    IPC: G06F9/50 ,  G06F15/76 ,  H04L51/226 ,  G06F15/17 ,  H04L61/59 ,  H04L67/2885

    Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

    Systems and methods to skip inconsequential matrix operations
    47.
    发明授权
    Systems and methods to skip inconsequential matrix operations 有权

    公开(公告)号：US11900114B2

    公开(公告)日：2024-02-13

    申请号：US17878427

    申请日：2022-08-01

    Applicant: Intel Corporation

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  William Rash ,  Subramaniam Maiyuran ,  Varghese George ,  Rajesh Sankaran

    IPC: G06F9/30

    CPC classification number: G06F9/30069 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30083 ,  G06F9/30101

    Abstract: Disclosed embodiments relate to systems and methods to skip inconsequential matrix operations. In one example, a processor includes decode circuitry to decode an instruction having fields to specify an opcode and locations of first source, second source, and destination matrices, the opcode indicating that the processor is to multiply each element at row M and column K of the first source matrix with a corresponding element at row K and column N of the second source matrix, and accumulate a resulting product with previous contents of a corresponding element at row M and column N of the destination matrix, the processor to skip multiplications that, based on detected values of corresponding multiplicands, would generate inconsequential results; scheduling circuitry to schedule execution of the instruction; and execution circuitry to execute the instructions as per the opcode.

    VIRTUALIZATION OF INTERPROCESSOR INTERRUPTS
    50.
    发明申请
    VIRTUALIZATION OF INTERPROCESSOR INTERRUPTS 有权

    公开(公告)号：US20220365802A1

    公开(公告)日：2022-11-17

    申请号：US17561433

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Gilbert Neiger ,  Rajesh Sankaran ,  Hisham Shafi

    IPC: G06F9/455 ,  G06F13/24

    Abstract: Embodiments of apparatuses, methods, and systems for virtualization of interprocessor interrupts are disclosed. In an embodiment, an apparatus includes a plurality of processor cores; an interrupt controller register; and logic to, in response to a write from a virtual machine to the interrupt controller register, record an interprocessor interrupt in a first data structure configured by a virtual machine monitor and send a notification of the interprocessor interrupt to at least one of the plurality of processor cores.

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