公开(公告)号：DE3855930D1

公开(公告)日：1997-07-10

申请号：DE3855930

申请日：1988-03-25

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  MUSUMECI SALVATORE

IPC: H01L21/8222 ,  H01L21/8248 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/082 ,  H02P7/00 ,  H02P7/288 ,  H01L27/088

公开(公告)号：DE3855603D1

公开(公告)日：1996-11-14

申请号：DE3855603

申请日：1988-12-16

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/739 ,  H01L29/78 ,  H01L29/72 ,  H01L21/82

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

公开(公告)号：IT8922428D0

公开(公告)日：1989-11-17

申请号：IT2242889

申请日：1989-11-17

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  PALARA SERGIO

IPC: H01L21/331 ,  H01L29/73 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732 ,  H01L

Abstract: The monolithic vertical-type semiconductor power device comprises an N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which there is obtained aP type insulation pocket (3). Such pocket contains N type regions (4, 15) and P type regions (8) which in turn contain N+ type regions (11, 12; 13; 14) and of P type regions (6, 7, 9, 10) which define circuit components (T1, T2, T5) of the device. Insulation pocket (3) is wholly covered by a first metallisation (21, 30) connected to ground. Such metallisation (21, 30) is in turn protected by a layer of insulating material (18) suitable for allowing the crossing of metal tracks (20) or of a second metallisation (31) for the connection of the different components.

公开(公告)号：DE3855930T2

公开(公告)日：1997-12-18

申请号：DE3855930

申请日：1988-03-25

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  MUSUMECI SALVATORE

IPC: H01L21/8222 ,  H01L21/8248 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/082 ,  H02P7/00 ,  H02P7/288 ,  H01L27/088

公开(公告)号：DE69109468D1

公开(公告)日：1995-06-08

申请号：DE69109468

申请日：1991-05-23

Applicant: SGS THOMSON MICROELECTRONICS ,  ANSALDO TRASPORTI SPA

Inventor： FERLA GIUSEPPE ,  RONSISVALLE CESARE ,  ZANI PIER ENRICO

IPC: H01L25/07 ,  H01L23/051 ,  H01L23/50 ,  H01L23/525 ,  H01L25/18 ,  H01L23/522

公开(公告)号：DE68918390T2

公开(公告)日：1995-03-02

申请号：DE68918390

申请日：1989-10-26

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BALLARO' DAVID ,  PATTI ALFONSO ,  FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/732

Abstract: The emitter region of the speed-up transistor is created in the base of the final transistor of the Darlington device and has a very low dope concentration and thickness.

公开(公告)号：IT1236994B

公开(公告)日：1993-05-12

申请号：IT2289189

申请日：1989-12-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L

Abstract: Process for the manufacture of power-MOS semiconductor devices which achieve high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall (FIG. 11).