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    MOS TECHNOLOGY POWER DEVICE
    1.
    发明专利
    MOS TECHNOLOGY POWER DEVICE 失效

    公开(公告)号：JPH09252115A

    公开(公告)日：1997-09-22

    申请号：JP28875896

    申请日：1996-10-30

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To make the contact of source metal layers and main body areas satisfactory even if scaled down to the limit of photolithography and to realize high integration. SOLUTION: Respective basic function unit contain second conductive long main body areas 3 being parallel bars which are formed in a semiconductor material layer and are detached by the distance (d). Main body parts 40 to which first conductive impurities are not given and first conductive source areas 60 are mutually positioned in the respective long main body areas 3. Openings 11 are provided for dielectric layers 9 sealing the conductive layers to be grown to gates along the center parts of the long main body areas 3. The metal layers constituting a source electrode are brought into contact with the source areas 60 and the main body parts 40.

    MOS TECHNIQUE POWER DEVICE
    2.
    发明专利
    MOS TECHNIQUE POWER DEVICE 失效

    公开(公告)号：JPH09298301A

    公开(公告)日：1997-11-18

    申请号：JP28872996

    申请日：1996-10-30

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： FRISINA FERRUCCIO ,  MAGRI ANGELO ,  FERLA GIUSEPPE

    IPC: H01L29/74 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/749 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a power device with a higher integration scale than a conventional MOS technique power device. SOLUTION: This device is provided with a conductive insulating gate layer covering a first conductivity type semiconductor layer and a plurality of basic function unit. Each basic function unit contains a slim window formed on an insulating gate layer 9 extending on a slim base body 3. The first conductivity type source regions 60 not doped with impurities of the main parts 40 are alternately positioned in each slim base body 3. Further, a side wall spacer of an insulating material is formed along a longitudinally directed edge of each slim window so as to seal an edge of each slim window. A source metal layer is brought into contact with each slim main body region and each source region through each main body region.

    4.
    发明专利
    未知

    公开(公告)号：DE3855603D1

    公开(公告)日：1996-11-14

    申请号：DE3855603

    申请日：1988-12-16

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/739 ,  H01L29/78 ,  H01L29/72 ,  H01L21/82

    Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

    6.
    发明专利
    未知

    公开(公告)号：DE3855603T2

    公开(公告)日：1997-03-13

    申请号：DE3855603

    申请日：1988-12-16

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/739 ,  H01L29/78 ,  H01L29/72 ,  H01L21/82

    Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

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