公开(公告)号：JPH09298301A

公开(公告)日：1997-11-18

申请号：JP28872996

申请日：1996-10-30

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  MAGRI ANGELO ,  FERLA GIUSEPPE

IPC: H01L29/74 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/749 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a power device with a higher integration scale than a conventional MOS technique power device. SOLUTION: This device is provided with a conductive insulating gate layer covering a first conductivity type semiconductor layer and a plurality of basic function unit. Each basic function unit contains a slim window formed on an insulating gate layer 9 extending on a slim base body 3. The first conductivity type source regions 60 not doped with impurities of the main parts 40 are alternately positioned in each slim base body 3. Further, a side wall spacer of an insulating material is formed along a longitudinally directed edge of each slim window so as to seal an edge of each slim window. A source metal layer is brought into contact with each slim main body region and each source region through each main body region.

公开(公告)号：JPH09252115A

公开(公告)日：1997-09-22

申请号：JP28875896

申请日：1996-10-30

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To make the contact of source metal layers and main body areas satisfactory even if scaled down to the limit of photolithography and to realize high integration. SOLUTION: Respective basic function unit contain second conductive long main body areas 3 being parallel bars which are formed in a semiconductor material layer and are detached by the distance (d). Main body parts 40 to which first conductive impurities are not given and first conductive source areas 60 are mutually positioned in the respective long main body areas 3. Openings 11 are provided for dielectric layers 9 sealing the conductive layers to be grown to gates along the center parts of the long main body areas 3. The metal layers constituting a source electrode are brought into contact with the source areas 60 and the main body parts 40.

公开(公告)号：DE69109468T2

公开(公告)日：1995-12-14

申请号：DE69109468

申请日：1991-05-23

Applicant: SGS THOMSON MICROELECTRONICS ,  ANSALDO TRASPORTI SPA

Inventor： FERLA GIUSEPPE ,  RONSISVALLE CESARE ,  ZANI PIER ENRICO

IPC: H01L25/07 ,  H01L23/051 ,  H01L23/50 ,  H01L23/525 ,  H01L25/18 ,  H01L23/522

公开(公告)号：ITMI910836D0

公开(公告)日：1991-03-28

申请号：ITMI910836

申请日：1991-03-28

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/22 ,  H01L29/73 ,  H01L21/322 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/732 ,  H01L29/861 ,  H01L

Abstract: The structure consists of a single chip (1) of semiconductor material, which comprises an area (32) having a high lifetime of the minority carriers, which constitutes a bipolar power device with high current density, and at least one area (20, 21; 20', 21') with a reduced lifetime of the minority carriers, which constitutes a fast diode.

公开(公告)号：IT8922891D0

公开(公告)日：1989-12-29

申请号：IT2289189

申请日：1989-12-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  MAGRO CARMELO ,  LANZA PAOLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L

Abstract: Process for the manufacture of power-MOS semiconductor devices which achieve high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall (FIG. 11).

公开(公告)号：IT8921281D0

公开(公告)日：1989-07-24

申请号：IT2128189

申请日：1989-07-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  LANZA PAOLO ,  MAGRO CARMELO

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/265 ,  H01L21/32 ,  H01L21/336

Abstract: Along the outline of a first doped region of a first mask is formed using the spacer technology, said mask being made up of a dielectric opposing to the oxygen diffusion. Another mask is created within this first mask, using a process of selective thermal oxidation. The second mask is used to implant dopant into a second region which will only be defined along the outlines of the first region.

公开(公告)号：DE3855603T2

公开(公告)日：1997-03-13

申请号：DE3855603

申请日：1988-12-16

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/739 ,  H01L29/78 ,  H01L29/72 ,  H01L21/82

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

公开(公告)号：DE69007449T2

公开(公告)日：1994-08-25

申请号：DE69007449

申请日：1990-12-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  MAGRO CARMELO ,  LANZA PAOLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/784

Abstract: Process for the manufacture of power-MOS semiconductor devices which achieve high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall (FIG. 11).

公开(公告)号：DE69007449D1

公开(公告)日：1994-04-21

申请号：DE69007449

申请日：1990-12-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  MAGRO CARMELO ,  LANZA PAOLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/784

Abstract: Process for the manufacture of power-MOS semiconductor devices which achieve high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall (FIG. 11).

公开(公告)号：IT1231300B

公开(公告)日：1991-11-28

申请号：IT2128189

申请日：1989-07-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FERLA GIUSEPPE ,  LANZA PAOLO ,  MAGRO CARMELO

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/265 ,  H01L21/32 ,  H01L21/336 ,  H01L

Abstract: Along the outline of a first doped region of a first mask is formed using the spacer technology, said mask being made up of a dielectric opposing to the oxygen diffusion. Another mask is created within this first mask, using a process of selective thermal oxidation. The second mask is used to implant dopant into a second region which will only be defined along the outlines of the first region.