公开(公告)号：DE69421606D1

公开(公告)日：1999-12-16

申请号：DE69421606

申请日：1994-03-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO

IPC: H01L29/73 ,  H01L21/22 ,  H01L21/331 ,  H01L29/732

Abstract: A manufacturing process for obtaining integrated structure bipolar transistors with controlled storage time comprises the steps of: in a silicon material (1, 2), forming at least one bipolar transistor occupying a first area (AD) on a first surface of the silicon material (1, 2); covering the first surface of the silicon material (1, 2) with an insulating material layer (5); selectively removing the insulating material layer (5) to open at least one window (6) having a second area (APt) much smaller than the first area (AD) occupied by the bipolar transistor; implanting into the silicon material (1, 2) a medium dose (D) of platinum ions through said window (6); and diffusing into the silicon material (1, 2) the implanted platinum ions to obtain a uniform distribution of platinum inside the transistor.

公开(公告)号：DE69321966T2

公开(公告)日：1999-06-02

申请号：DE69321966

申请日：1993-12-24

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  MANGIAGLI MARCANTONIO

IPC: H01L27/04 ,  H01L21/60 ,  H01L21/822 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78 ,  H01L27/105

Abstract: An integrated structure pad assembly for lead bonding to a power semiconductor device chip comprises a chip portion having a top surface covered by a metallization layer (10) and which comprises a first sub-portion (1) wherein functionally active elements of the power device are present; said chip portion comprises at least one second sub-portion (11) wherein no functionally active elements of the power device are present, and a top surface of the metallization layer (10) is elevated over said at least one second sub-portion (11) with respect to the first sub-portion (1) to form at least one protrusion which forms a support surface for a lead.

公开(公告)号：DE69117889D1

公开(公告)日：1996-04-18

申请号：DE69117889

申请日：1991-11-16

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  TAVOLO NELLA ,  RASPAGLIESI MARIO

IPC: H01L21/322 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/167

公开(公告)号：DE3855603D1

公开(公告)日：1996-11-14

申请号：DE3855603

申请日：1988-12-16

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/739 ,  H01L29/78 ,  H01L29/72 ,  H01L21/82

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

公开(公告)号：DE3855603T2

公开(公告)日：1997-03-13

申请号：DE3855603

申请日：1988-12-16

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/739 ,  H01L29/78 ,  H01L29/72 ,  H01L21/82

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

公开(公告)号：DE68918390T2

公开(公告)日：1995-03-02

申请号：DE68918390

申请日：1989-10-26

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BALLARO' DAVID ,  PATTI ALFONSO ,  FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/732

Abstract: The emitter region of the speed-up transistor is created in the base of the final transistor of the Darlington device and has a very low dope concentration and thickness.