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公开(公告)号：DE602005002223T2
公开(公告)日：2008-05-21
申请号：DE602005002223
申请日：2005-10-27
Applicant: ST MICROELECTRONICS SA
Inventor： KARI AHMED , NAURA DAVID
Abstract: The method involves generating a edge detection signal (FD) from an encoded data signal (CD) and sampling four pulses of the edge detection signal in a manner to obtain a decoded binary data signal (BD). A binary clock signal (CLK) is generated from the detection signal, where the clock signal is synchronous with the encoded data signal, for changing a logic state of the pulses of the detection signal. An independent claim is also included for a device for decoding a binary encoded data signal and generating a clock signal synchronous with the encoded data signal.
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公开(公告)号：FR2890483A1
公开(公告)日：2007-03-09
申请号：FR0509141
申请日：2005-09-08
Applicant: ST MICROELECTRONICS SA
Inventor： RIZZO PIERRE , MOREAUX CHRISTOPHE , NAURA DAVID , KARI AHMED
IPC: G11C14/00
Abstract: L'invention concerne une cellule mémoire volatile rémanente (PVCELL), pour mémoriser une donnée binaire (Fp) pendant un temps de rétention (Tp) indépendant d'une tension (Vcc) d'alimentation de la cellule mémoire. Selon l'invention, la cellule mémoire comprend un point mémoire capacitif (CMP) fournissant une tension rémanente (Vp) et ayant un temps de décharge déterminé, un interrupteur (T1) pour provoquer la décharge du point mémoire lorsqu'un signal d'effacement (RESET) présente une valeur active, un interrupteur (T2) pour provoquer la charge du point mémoire lorsqu'un signal d'écriture (SET) présente une valeur active, et un circuit détecteur-amplificateur (SACT) ayant une entrée (IN1) recevant la tension rémanente (Vp), et une sortie (OUT1) fournissant la donnée binaire (Fp). Application notamment à la gestion d'un drapeau d'inventaire dans un circuit intégré sans contact.
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公开(公告)号：FR2877520A1
公开(公告)日：2006-05-05
申请号：FR0411754
申请日：2004-11-04
Applicant: ST MICROELECTRONICS SA
Inventor： KARI AHMED , NAURA DAVID
Abstract: Procédé pour décoder un signal de données binaires codées (CD) et pour générer un signal d'horloge (CLK) synchrone avec le signal de données codées, chaque donnée binaire du signal de données codées ayant une durée prédéfinie (t0), et selon son état binaire la forme d'une période ou deux périodes d'un signal carré périodique, le procédé consistant à : générer à partir du signal de données codées (CD) un signal de détection de fronts (FD) comportant quatre impulsions par état binaire du signal de données codées, échantillonner le signal de données codées toutes les quatre impulsions du signal de détection de fronts, de manière à obtenir un signal binaire (BD) de données décodées, et générer à partir du signal de détection de fronts, un signal binaire d'horloge (CLK) synchrone avec le signal de données codées (CD), présentant un changement d'état logique toutes les deux impulsions du signal de détection de fronts.
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公开(公告)号：FR2858457A1
公开(公告)日：2005-02-04
申请号：FR0309456
申请日：2003-07-31
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , BERTRAND BERTRAND , CHEHADI MOHAMAD
Abstract: The method involves applying a memory cell state fixation pulse on a floating gate of a transistor of the cell of a non-volatile memory. A high voltage signal for adjusting the cell state fixing portion is applied on a ramp voltage generation circuit (301) of the memory from outside the memory at a preset duration. The cell state fixing portion is adjusted at the preset duration. An independent claim is also included for a non volatile memory.
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公开(公告)号：FR2854967A1
公开(公告)日：2004-11-19
申请号：FR0305742
申请日：2003-05-13
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , BERTRAND BERTRAND , CHEHADI MOHAMAD
Abstract: Device, such as semiconductor memory or EEPROM, communicates following a communication protocol that forecasts transmission of acknowledgement signals (ACK) at predefined instants. The operating mode is identified by a shift in time of the moment of transmission of the ACK signal relative to the forecast moment. An independent claim is also included for a device for identifying the mode of operation of a device.
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Patent Agency Ranking
公开(公告)号：FR2853781A1
公开(公告)日：2004-10-15
申请号：FR0304365
申请日：2003-04-09
Applicant: ST MICROELECTRONICS SA
Inventor： BERTRAND BERTRAND , CHEHADI MOHAMAD , NAURA DAVID
IPC: H03K3/011 , H03K3/012 , H03K3/3565
Abstract: The trigger has a latch with four transistors, where latch has two thresholds, and an input (IN) and an output (OUT) for forming an input and an output of the trigger. The latch also has a middle point between a supply terminal and an output of the latch. A negative feedback acts on the middle point to fix one of the thresholds according to supply potential. One threshold is a function of a stable reference potential.
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公开(公告)号：DE60003989T2
公开(公告)日：2004-05-06
申请号：DE60003989
申请日：2000-09-15
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , ZINK SEBASTIEN , BERTRAND BERTRAND
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公开(公告)号：DE60003989D1
公开(公告)日：2003-08-28
申请号：DE60003989
申请日：2000-09-15
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , ZINK SEBASTIEN , BERTRAND BERTRAND
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公开(公告)号：FR2821974B1
公开(公告)日：2003-05-23
申请号：FR0103284
申请日：2001-03-12
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , BERTRAND BERTRAND , CHEHADI MOHAMAD
Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.
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公开(公告)号：FR2799045B1
公开(公告)日：2002-02-08
申请号：FR9912150
申请日：1999-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: The integrated circuit memory is of EEPROM type, comprising the data input (D1) and the data output (DO), a planar memory (MM) organized inn words memory (M0-M7), a set of columns registers (LAT) associated with words memory, the first means regarding the write operation for loading the binary data of binary word received at the data input directly to latches (HV0-HV7) of columns register associated with the words memory, and the second means regarding the read operation for a successive reading of binary data stored in the memory cells of words memory and a direct delivery of each binary data in serial form to the data output. The latches for storage and switching (HV0-HV7) comprise each two inverters in antiparallel connection for the storage of binary datum in the form of higher programming voltage or the zero voltage, coupled to the means for conditional switching in the form of two transistors connected in series for carrying the higher programming voltage to the determined bit line, and the loading means in the form of two transistors with the common source connection. The first and second means also comprise the means for an application of selection signals (Bit0-Bit7) to the loading means of latches of each columns register, and the means for loading the data into latches which act via the register selection means in the form of a transistor common to all the latches of the determined columns register. The means for the loading data into latches are common to all columns registers of the memory. The second means comprise a single read line, READLINE, connecting the set of columns registers (LAT) to a read circuit, SENSEAMP. The read circuit comprises only one read amplifier to detect a current flowing in the read line. The memory comprises only one output data line, OUTPUTDATALINE, connecting the output of read circuit to the data output (DO) via a buffer circuit, OUTBUF. The first means comprise only one input data line, INPUTDATALINE, connecting the data input (DI) to the set of columns registers (LAT) via a buffer circuit, INBUF.
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