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41.发明专利
公开(公告)号：FR2875352A1
公开(公告)日：2006-03-17
申请号：FR0409650
申请日：2004-09-10
Applicant: ST MICROELECTRONICS SA
Inventor： GENDRIER PHILIPPE , CANDELIER PHILIPPE , FOURNEL RICHARD
Abstract: La mémoire stocke des blocs-codes comportant des données d'informations et des données de contrôle. Le procédé comprend une lecture de chaque élément d'un bloc-code comportant une comparaison du courant délivré par la cellule-mémoire stockant cet élément avec un courant de référence, et un décodage du bloc-code ainsi lu délivrant une information représentative du nombre d'erreurs dans le bloc-code lu. En présence d'un nombre d'erreurs supérieur à un,a) on modifie la valeur du courant de référence (Iref) d'un pas choisi, etb) on effectue de nouveau une lecture et un décodage du bloc-code de façon à obtenir une nouvelle information d'erreur, eton réitère éventuellement les phases a) et b) jusqu'à obtenir un nombre final d'erreurs au plus égal à un.En variante on peut modifier dans l'étape a) l'instant d'enregistrement des données lors de l'opération de lecture.
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公开(公告)号：FR2869445A1
公开(公告)日：2005-10-28
申请号：FR0450779
申请日：2004-04-26
Applicant: ST MICROELECTRONICS SA , CENTRE NAT RECH SCIENT , UNIV PARIS SUD
Inventor： KIM JOO VON , DEVOLDER THIBAUT , CHAPPERT CLAUDE , MAUFRONT CEDRIC , FOURNEL RICHARD
Abstract: L'invention concerne un élément mémoire magnétorésistif (16) comprenant une région magnétique piégée (22) et une région magnétique libre (18) séparées par une couche barrière (20). La région magnétique libre comprend un empilement d'au moins deux couches ferromagnétiques (26, 28) couplées antiferromagnétiquement, à chaque couche étant associé un vecteur moment magnétique de couche ( 1, 2), le vecteur moment magnétique résultant, égal à la somme des vecteurs moment magnétique de couche, ayant une amplitude inférieure à au moins 40% de l'amplitude du vecteur moment magnétique de couche d'amplitude maximale. Le champ d'anisotropie ou le tenseur de champ démagnétisant n'est pas identique pour les deux couches ferromagnétiques d'où il résulte que les déviations angulaires des vecteurs moment magnétique de couche sont différentes au moment de l'application d'un champ magnétique extérieur, ce qui permet au moins deux procédés d'écriture directe de l'élément mémoire ainsi que son initialisation.
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公开(公告)号：FR2838563B1
公开(公告)日：2004-07-09
申请号：FR0204690
申请日：2002-04-15
Applicant: ST MICROELECTRONICS SA
Inventor： GENDRIER PHILIPPE , DRAY CYRILLE , FOURNEL RICHARD
IPC: H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , G11C16/02
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公开(公告)号：FR2783941B1
公开(公告)日：2004-03-12
申请号：FR9812200
申请日：1998-09-30
Applicant: ST MICROELECTRONICS SA
Inventor： FOURNEL RICHARD
Abstract: A regulation circuit for regulating an output voltage of a positive charge pump for an integrated circuit includes a comparison circuit receiving a reference voltage at an input, and delivering an enabling signal at an output to the positive charge pump. The regulation circuit further includes a first switching circuit controlled by a first control signal for the application of a first voltage level as a reference voltage when the integrated circuit is in an operational mode, and the application of a second voltage level as the reference voltage when the integrated circuit is in a standby mode.
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公开(公告)号：FR2838563A1
公开(公告)日：2003-10-17
申请号：FR0204690
申请日：2002-04-15
Applicant: ST MICROELECTRONICS SA
Inventor： GENDRIER PHILIPPE , DRAY CYRILLE , FOURNEL RICHARD
IPC: H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , G11C16/02
Abstract: The semiconductor memory device comprises a transistor with a floating gate (FG) and a control gate formed by the regions of source (S), drain (D) and channel of the transistor. The memory cell comprises a dielectric zone (ZTN) laid out between a first part (P1) of the layer of gate material and a first active zone (RG1) electrically insulated from a second active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate towards the first active zone at the time of erasing the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) extended between the first part and the ring gate. The first active zone (RG1) and the second active zone (RG2) are electrically insulated one from the other by the p-n junctions polarized in reverse, and on the surface by a region of shallow trench isolation (STI). The two regions of substrate (RG1,RG2) are of the first conductivity type, and the intermediate region (RG3) is of the second conductivity type. The isolation region (RG3) comprises an opening for a contact zone (PSB). The first region of substrate (RG1) comprises a contact zone (PC1) of the first conductivity type. The device also comprises the polarization means possessing the states of programming, reading and erasing the memory cell. The erasing of type Fowler-Nordheim is by applying a voltage to the first active zone much higher than to the regions of source, drain and substrate of the transistor. The programming is by hot carriers at the level of transistor. The programming of type Fowler-Nordheim is by applying to the region of source, drain and substrate the voltages much higher than to the first active zone. The device comprises a memory array incorporating several memory cells, where each memory cell is associated with an access transistor. An integrated circuit comprises the device as claimed.
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Patent Agency Ranking
公开(公告)号：FR2811164B1
公开(公告)日：2003-08-29
申请号：FR0008546
申请日：2000-06-30
Applicant: ST MICROELECTRONICS SA
Inventor： FOURNEL RICHARD
Abstract: The integrated circuit (1) with supply voltages including a reference voltage as the ground (Gnd), a logic voltage (Vdd) and a higher voltage (HV) comprises a protection device (2) associated with at least one element with the gate oxide for applying to a supply node (N) either the logic voltage in the conditions of normal functioning of integrated circuit, or the higher voltage in the conditions of abnormal functioning for breaking down the gate oxide to make the integrated circuit irreversibly unusable. The integrated circuit comprises means (4) for the detection of abnormal conditions for activating an alarm signal (IN) which is applied to the control input of the protection device (2). The protection device contains two switches functioning in complementary manner for applying the higher voltage or the logic voltage to the supply node (N), and a voltage translator with at least one cascade stage providing signals for the control of switches. The voltage translator contains in eahc of two branches a transistor connected to the higher voltage, a transistor connected to the ground, and at least one cascade transistor connected between the two transistors. The supply node (N) is for the application of logic voltage, and the higher voltage is applied to an external pin, or the higher voltage is delivered internally on the basis of logic voltage. The method for the protection of integrated circuit against abnormal uses includes an application of higher voltage instead of logic voltage to at least one logic element of integrated circuit.
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公开(公告)号：FR2820545B1
公开(公告)日：2003-05-30
申请号：FR0101442
申请日：2001-02-02
Applicant: ST MICROELECTRONICS SA
Inventor： FOURNEL RICHARD , SEDJAI LEILA
IPC: G11C16/34 , G11C29/34 , H01L21/8247
Abstract: An electrical state of a group of N cells of a non-volatile memory are simultaneously checked. The group of N memory cells to be checked, along with a checking cell, are simultaneously selected and read. The N signals read are summed to obtain a summed signal. The summed signal is compared with the signal read from the checking cell to-provide a first state signal when the summed signal is less than the signal read from the checking cell. This indicates that the N memory cells are in a first electrical state. If a second state signal is provided in the comparison, this indicates that at least one memory cell is not in the first electrical state when the summed signal is greater than the signal read on the checking cell.
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公开(公告)号：FR2824413A1
公开(公告)日：2002-11-08
申请号：FR0106091
申请日：2001-05-07
Applicant: ST MICROELECTRONICS SA
Inventor： DRAY CYRILLE , FOURNEL RICHARD , THOMAS SIGRID
Abstract: The memory store is organized in words according to an array of rows and columns, and the selection of a word is ensured by the signals for selecting a row and a column (Selrow,Selcol), where the signals are delivered by two address decoders (DECX,DECYm). Each memory-cell word (M0,0) regroups several, in particular 8 for 8-bit word, memory cells (C0,...,C7) on the same row, and each cell comprises a memory transistor of MOS type with a control gate and two channel electrodes the drainn and the source; the control gates of the cells of each row are connected together to a gate control line (CG0), and the drain of each cell is connected to the respective bit line (B10,...,B17). Each word comprises a word-selecting transistor (TS0,0) by the source, and is controlled by the low-voltage selection signals (SelRow,SelCol). The gate control lines (CG0,...Cgm-1) are controlled by a polarization circuit (1) receiving the address selection signals. The gate control lines are regrouped at least two by two, and each group is controlled by a higher-voltage switching circuit of the polarization circuit. The gate control lines put together correspond to the to the neighbouring rows. The higher-voltage switching circuit applies either the higher voltage (Vpp) in the case of the write instruction, or a stationary voltage (Vrepos) applied outside of the write operation. The level of stationary voltage is chosen as equal to the level of polarization voltage in the read mode. Each column of memory store comprises bit lines (B10,...,B17), connected to a write circuit (2) for writing (DATA-IN) and to a read circuit (3) for reading (DATA-OUT). The read circuit (3) comprises a precharge circuit associated with a detection circuit comprising differential amplfiers, and the precharge circuit receives an activation instruction before the start of a cycle or a succession of cycles of the read operations. The precharge circuit brings all bit lines to the same precharge voltage (Vpch). The memory store comprises an isolating circuit (EI) between the bit lines and the read circuit (3), which is activated during the write operations. An integrated circuit comprises the read-only memory store of specified architecture.
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公开(公告)号：FR2823900A1
公开(公告)日：2002-10-25
申请号：FR0105343
申请日：2001-04-20
Applicant: ST MICROELECTRONICS SA
Inventor： DRAY CYRILLE , FOURNEL RICHARD
IPC: G11C16/04 , H01L27/115 , H01L29/66
Abstract: The memory store comprises one or more cells (C1,C2,C3) where each cell contains a transistor of type FAMOS (T1) whose gate is insulated, and two access transistors (T2,T3) whose respective gates, sources and drains are connected together. The drains of the access transistors (T2,T3) are connected to the source of the insulated-gate transistor (T1). An isolating transistor (T4) is connected between two neighbouring cells (C1,C2) so that the drain and the source are connected to the sources of the insulated-gate transistors of the neighbouring cells of the same word line (WL). The drain of the insulated-gate transistor (T1) is connected to the associated bit line (BL1). The gates of the access transistors (T2,T3) are connected to the word line (WL), and the sources are connected to a supply line (SL). The insulating transistor (T4) and the access transistors (T2,T3) of all cells have a common gate. The insulated-gate transistor (T1) and the access transistors (T2,T3) of the first or the second cell on one hand, and the isolating transistor (T4) on the other hand, are implemented in the same well. The insulated-gate transistor has a ring structure which comprises a central diffusion zone, a peripheral diffusion zone, and an intermediate polysilicon zone. The structure also comprises a separation zone which includes a bar substantially perpendicular to an axis passing through the centres of the cells, and barriers substantially parallel to the axis. A memory store comprises M x N insulated-gate transistors having ring structure which are laid-out in N rows and M columns, where the central diffusion zone forms the drain and the peripheral diffusion zone forms the source of the insulated-gate transistors; for each row the separation zone separates M insulated-gate transistors and comprises two barriers substantially parallel to the axis of the insulated-gate transistors, and M-1 bars perpendicular to the barriers. The separation zones of rows of ranks n and n+1 where n is an integer from N to N-1, have a contact line in common situated between the two barriers.
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公开(公告)号：FR2820539A1
公开(公告)日：2002-08-09
申请号：FR0101440
申请日：2001-02-02
Applicant: ST MICROELECTRONICS SA
Inventor： FOURNEL RICHARD , SEDJAI LEILA
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