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    42.
    发明专利
    未知

    公开(公告)号：DE602006011005D1

    公开(公告)日：2010-01-21

    申请号：DE602006011005

    申请日：2006-08-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI

    IPC: G11C16/08 ,  G11C8/08

    Abstract: A non-volatile memory device is provided. The memory device includes a memory matrix (105; 605) comprising a plurality of memory cells (Mc), arranged according to a plurality of rows and a plurality of columns. The memory device further includes a plurality of word lines (WL(i)); each word line is associated with one respective row of said plurality and is connected to the memory cells of the row; the word lines are grouped into at least one packet (WLP). The memory device includes a row selector (160; 660) coupled to the word lines and adapted to selectively biasing them. The row selector includes, for each packet of word lines, a plurality of first paths, wherein each first path is adapted to apply a first biasing voltage to a corresponding word line of the packet depending on an operation to be performed on the memory cells connected to the corresponding word line. Each first path includes at least a first (N(i)) and a second (P(i)) selection transistors series-connected between a first terminal and a second terminal of the first path. The second terminal is coupled to the corresponding word line. The memory device further includes enabling means (110) for commonly providing an enabling voltage to the first terminal of the first paths associated to a selected packet of word lines including a selected word line. The enabling voltage depends on the operation to be performed on the memory cells connected to the selected word line and is adapted to enable the execution of said operation. The memory device further includes selection means (150) for selecting one among said plurality of first paths. the selected first path corresponding to the selected word line. The selection means are adapted to activate the first selection transistor of the selected first path in order to obtain the first biasing voltage from the enabling voltage by a voltage drop introduced by the first selection transistor; said selection means are further adapted to activate the second selection transistor of the selected first path in order to transfer the first biasing voltage provided by the first selection transistor onto the selected word line.

    45.
    发明专利
    未知

    公开(公告)号：DE69820594D1

    公开(公告)日：2004-01-29

    申请号：DE69820594

    申请日：1998-05-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MAURELLI ALFONSO

    IPC: G11C16/06 ,  G11C7/06 ,  G11C16/28

    Abstract: The reading method comprises the steps of: supplying simultaneously two memory cells (F1, F2), both storing a respective unknown charge condition; generating two electrical quantities (Va, Vb), each correlated to a respective charge condition; comparing the two electrical quantities (Va, Vb) with each other; and generating a two-bit signal (01, 02) on the basis of the result of the comparison. The reading circuit comprises a two-input comparator (58) comprising two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter (41). Both the two-input comparator (58) and the current/voltage converter (41) comprise low threshold transistors (49, 50, 65-68).

    47.
    发明专利
    未知

    公开(公告)号：DE69524572D1

    公开(公告)日：2002-01-24

    申请号：DE69524572

    申请日：1995-04-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28

    Abstract: A sense amplifier circuit for a semiconductor memory device comprises first current/voltage conversion means (1) for converting a current of a memory cell (MC) to be read into a voltage signal (V9), second current voltage/conversion means (2) for converting a reference current into a reference voltage signal (V20), and voltage comparator means (3) for comparing the voltage signal (V9) with the reference voltage signal (V20); the sense amplifier circuit comprises capacitive decoupling means (C1) for decoupling the voltage signal (V9) from the comparator means (3), and means (13) for providing the capacitive decoupling means (C1) with an electric charge suitable for compensating an offset voltage introduced in the voltage signal (V9) by an offset current superimposed on the current of the memory cell (MC) to be read.

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