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    42.
    发明专利
    未知

    公开(公告)号：DE69514523D1

    公开(公告)日：2000-02-17

    申请号：DE69514523

    申请日：1995-10-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO

    IPC: H02M3/07

    Abstract: A regulating circuit for the output voltage of a voltage booster, of the type which comprises a first charge transfer capacitor (C1) adapted to draw electric charges from the supply terminal (2) and transfer them to the output terminal (3), through electronic switches controlled by non-overlapped complementary phase signals, and a second charge storage capacitor (C2) connected between the output terminal (3) and ground (GND), further comprises an error amplifier which generates, during one of the operational phases, a DC voltage corresponding to the difference between a reference voltage (Vrif) and a voltage (Vx) being a duplicate of the output voltage (Vout) of the voltage booster; this DC voltage is applied directly to one end of the transfer capacitor (C1).

    49.
    发明专利
    未知

    公开(公告)号：DE69707666T2

    公开(公告)日：2002-08-08

    申请号：DE69707666

    申请日：1997-08-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  CONFALONIERI PIERANGELO

    IPC: H03M1/08 ,  H03H11/04 ,  H03H11/12 ,  H03H1/00

    Abstract: An area-efficient low-pass, time-invariant, second-order reconstruction filter, particularly for current-driven digital-to-analog converters, comprising: a first resistor (R1) and a first capacitor (C1) which are parallel connected; an operational amplifier (3); a terminal of a second resistor (R2) which is connected to the inverting input of the operational amplifier; another terminal of the second resistor which is connected to a common node of the first resistor (R1) and the first capacitor (C1); a second capacitor (C2), which is fedback between the output of the operational amplifier and the inverting input; the filter further comprising an additional pair of resistors (R3A, R3B) which are arranged so as to be fedback between the output and the inverting input, a current signal (IDAC) arriving from a digital-to-analog converter arranged upstream of the reconstruction filter being fed to a common node of the additional pair of resistors.

    50.
    发明专利
    未知

    公开(公告)号：DE69430525D1

    公开(公告)日：2002-06-06

    申请号：DE69430525

    申请日：1994-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  NICOLLINI GERMANO

    IPC: G06F1/24 ,  G11C7/22 ,  H03K3/356 ,  H03K17/00 ,  H03K17/22 ,  G11C7/00

    Abstract: An initialization circuit for memory registers (2), being of the type which comprises a signal input (I) being applied a supply voltage (Vp) which rises linearly from a null value, and an initializing output (O) connected to an input of a memory register (2) and on which a voltage signal (Vd) being equal or proportional to the supply voltage (Vp), during the initialization step, and a null voltage signal, upon the supply voltage (Vp) dropping below a predetermined tripping value (Vs), are produced, further comprises, between the input (I) and the output (O): a first circuit portion (3) connected to the input (I), a second circuit portion (4) connected after the first and having a first output (D) connected to the initializing output (O), and a third, inverting circuit portion (7) having an input connected to a second output (C) of the second portion (4) and an output (E) connected to the first portion to even hold off that first portion (3) while the supply voltage drops below the threshold voltage (Vs).

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