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    41.
    发明专利
    未知

    公开(公告)号：DE69427461T2

    公开(公告)日：2002-04-11

    申请号：DE69427461

    申请日：1994-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO

    IPC: G11C29/00 ,  G11C14/00 ,  G11C16/04 ,  G11C16/26 ,  G11C29/04 ,  G11C16/06

    Abstract: A non-volatile memory element with dual programmable cells and associated read circuit, which comprises a circuit (LATCH) of the bistable type connected between the two memory cells, to which it is coupled through first and second switching circuit elements (SW1, SW2). Such switching elements enable a single initial write step by one of the two memory cells only, and thereafter, enable connection of the clear cell and the programmed cell to the bistable circuit.

    42.
    发明专利
    未知

    公开(公告)号：DE60037504D1

    公开(公告)日：2008-01-31

    申请号：DE60037504

    申请日：2000-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO ,  ODDONE GIORGIO

    IPC: G11C16/28 ,  G11C11/56

    Abstract: The invention relates to a circuit structure (1) for reading data contained in an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix (2) of memory cells (3) and at least one reference cell (4) for comparison with a memory cell (3) during a reading phase. The reference cell (4) is incorporated in a reference cells sub-matrix (5) which is structurally independent of the matrix (2) of memory cells (3). Also provided is a conduction path between the matrix (2) and the sub-matrix (5), which path includes bit lines (b1ref) of the submatrix (5) of reference cells (4) extended continuously into the matrix (2) of memory cells (3)

    44.
    发明专利
    未知

    公开(公告)号：DE69930605D1

    公开(公告)日：2006-05-18

    申请号：DE69930605

    申请日：1999-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO

    IPC: G11C11/56

    Abstract: A method for reading a synchronous multilevel non-volatile memory with cell addresses which define a pair of memory cells on different planes of the multilevel memory and plane addresses which define the plane on which the memory cell defined by a memory cell address is to be read, its peculiarity being the fact that it comprises the steps of: switching the plane address (Az) a preset time interval after the switching of a memory address (Ax, Ay) and at the highest possible switching frequency; and reading in output from the memory the content of a memory location which corresponds to the memory address on planes alternatively indicated by the switching of the plane address.

    46.
    发明专利
    未知

    公开(公告)号：DE69730007D1

    公开(公告)日：2004-09-02

    申请号：DE69730007

    申请日：1997-03-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO

    IPC: G11C5/06 ,  G11C11/00

    Abstract: The present invention relates to a semiconductor integrated, storage circuit device (MEM) having at least a first enable terminal (CE) for enabling the device (MEM), and a first number of address terminals (A0-A19) for inputting an external address (EA) formed of a corresponding first number of bits (A0-A19). It comprises a plurality (MTX) of data storage elements which are addressable by an internal address (IA) formed of a second number of bits (A0-A20) larger than said first number, and further comprises address storage elements (BF1) which are coupleable with their inputs to said first enable terminal (CE) for storing additional address bits (A20); thus, the internal address (IA) is comprised of the external address (EA) and the additional address bits (A20).

    47.
    发明专利
    未知

    公开(公告)号：DE69632023D1

    公开(公告)日：2004-05-06

    申请号：DE69632023

    申请日：1996-01-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO

    IPC: G01R19/165 ,  H03K17/30 ,  H03K17/00

    Abstract: The circuit, in accordance with the present invention for detecting the presence at a signal input (IT) of a high voltage higher than a predetermined value and signaling it to a signal output (OT) through a logical type signal comprises one or more first transistors (P1-...) of type MOS and of a predetermined conductivity type each diode-connected and having its body terminal connected to the source terminal and having principal conduction paths connected in series for current conduction between a first node (ND1) and a ground input (GND) and two or more second transistors (P2-...) of the MOS type and of the same conductivity type each one diode-connected and having its body terminal connected to the source terminal and having principal conduction paths connected in series for current conduction between the signal input (IT) and the first node (ND1) and at least one first logical inverter (M1,M2) of the CMOS type having its input connected to the first node (ND1) and its output coupled to the signal output (OT) and connected for power supply to a power supply input (VDD) and to the ground input (GND).

    48.
    发明专利
    未知

    公开(公告)号：DE69631879D1

    公开(公告)日：2004-04-22

    申请号：DE69631879

    申请日：1996-04-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO

    IPC: H01L21/8247 ,  H01L27/105 ,  H01L21/00

    Abstract: A process for manufacturing an integrated circuit provides for the formation of a matrix of floating-gate non-volatile memory cells having dual polysilicon levels, with the two polysilicon levels being isolated by a gate dielectric layer (4) and an interpoly dielectric layer (9) therebetween, and for the concurrent formation of one type of thick-oxide transistor (7) in peripheral zones to the matrix. The process of the invention provides for removal, during the step of defining the first-level polysilicon (5) in order to form the floating-gate structures of the memory cells, of the polysilicon (5) from the active area zone of the thick-oxide transistor (7), so that the gate oxide of the transistor (7) results from the superposition of said first (4) and second (9) dielectric layers.

    49.
    发明专利
    未知

    公开(公告)号：DE69820032D1

    公开(公告)日：2004-01-08

    申请号：DE69820032

    申请日：1998-05-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO

    IPC: G11C16/02 ,  G11C11/00 ,  G11C11/56

    Abstract: A memory device comprising an array of memory cells (1), including at least one memory block (B0-B7) comprising multiple-level memory cells adapted for storing each one N ≥ 2 bits of information. The at least one memory block (B0-B7) also includes electrically erasable and programmable bilevel memory cells each one adapted for storing one bit of information, and means (2,5,3) are provided for either accessing and reading one of said multiple-level memory cell or simultaneously accessing and reading N of said electrically erasable and programmable bilevel memory cells, depending on address signals (A0-A21) supplied to the memory device.

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