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    READ CIRCUIT
    1.
    发明专利
    READ CIRCUIT 失效

    公开(公告)号：JPH08306190A

    公开(公告)日：1996-11-22

    申请号：JP22355395

    申请日：1995-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  GASTALDI ROBERTO ,  ROLANDI PAOLO ,  TORELLI GUIDO

    IPC: G11C11/419 ,  G11C7/06

    Abstract: PROBLEM TO BE SOLVED: To obtain a readout circuit which is used for a memory having a differential cell, and which can be used even in memory reading by a reference cell technique and improves a data read speed and low voltage operations. SOLUTION: A readout circuit has two leg parts SX, DX which are connected to between power source terminals Vdd and Vss , and each of the leg parts series- connects an electronic switch SW1 or SW2; a passive element T1 or T2 forming a voltage amplifier which is feedback-connected to a passive element T2 or T1 in another leg part; and a switch load element L1 or L2 to each other. Each of the passive elements is driven via a high impedance circuit element D1 or D2.

    VOLTAGE GENERATION CIRCUIT AND METHOD FOR OPERATION OF ELECTRIC LOAD ACCORDING TO VOLTAGE
    2.
    发明专利
    VOLTAGE GENERATION CIRCUIT AND METHOD FOR OPERATION OF ELECTRIC LOAD ACCORDING TO VOLTAGE 失效

    公开(公告)号：JPH0883493A

    公开(公告)日：1996-03-26

    申请号：JP23811794

    申请日：1994-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  GASTALDI ROBERTO ,  MALCOVATI PIERO ,  TORELLI GUIDO

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07 ,  H03K19/0175

    Abstract: PURPOSE: To obtain a voltage generation in a wide range and high reliability by a method wherein positive and negative voltages are generated by a voltage booster circuit and there are provided two 3-state logic gate circuits and additional 3-state logic gate circuit for operating a phase of a charge pump circuit incorporated in a booster. CONSTITUTION: Switch circuits (FFT1 to 6) comprise a 3-state logic gate circuit, boosters 7, 8 have command terminals ϕ1 , ϕ2 , a VDD terminal and a ground terminal, and when VDD is +5V, +10.5V and -10.5V. A booster 9 biases a substrate of a CMOS element of the booster 8. These are connected in a predetermined manner and gate capacitance C1 of a memory cell serves as a load. If a booster voltage is not acquired for the booster, an output is floated and the other boosters are nonactivated so as to occupy priority in common node control freely. With this structure, both positive and negative voltages for operating the memory cell via a control gate terminal are generated, an electrical load is operated, and selection in a wide IC technology and high reliability are obtained.

    3.
    发明专利
    未知

    公开(公告)号：DE69726136T2

    公开(公告)日：2004-08-26

    申请号：DE69726136

    申请日：1997-08-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  GASTALDI ROBERTO ,  CALLIGARO CRISTIANO

    IPC: G11C11/56 ,  G11C16/08 ,  G11C16/30 ,  G11C11/00 ,  G11C16/06

    Abstract: The present invention relates to a circuit for generating a regulated voltage (RV), in particular for gate terminals of non-volatile memory cells of the floating gate type, which comprises a generator circuit (OSC,CHP) adapted to generate an unregulated voltage (VCHP) on its output, a comparator circuit coupled to the output of the generator circuit (OSC,CHP), including a reference element consisting of a non-volatile memory cell (REFC) of the floating gate type and adapted to output an electric error signal (ID) tied to the difference between the unregulated voltage (VCHP) and the threshold voltage of the cell (REFC), and a regulator circuit (CSEL,CBIAS,IVC,DRV,TR) coupled to the output of the comparator circuit and operative to regulate the unregulated voltage (VCHP) based on the value of the electric error signal (ID). Through the present circuit, the regulated voltage (RV) is made programmable and tied to the parameters of the memory cell (REFC).

    4.
    发明专利
    未知

    公开(公告)号：DE69626804D1

    公开(公告)日：2003-04-24

    申请号：DE69626804

    申请日：1996-06-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  TELECCO NICOLA ,  TORELLI GUIDO

    IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  H03K5/13

    Abstract: A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block (RC) connected to an input terminal (ATD) for memory address line transition signals. The delay block drives a counter (CONT) which feedback controls the control block through a combinational logic circuit (COMB_SCA) connected to the output terminal (OUT_RC) of the programmable delay block. A logic output circuit (COMB_OUT), connected to the output terminal of the delay block and to the counter, generates the timing signals (OUT).

    10.
    发明专利
    未知

    公开(公告)号：DE69516402D1

    公开(公告)日：2000-05-25

    申请号：DE69516402

    申请日：1995-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  DANIELE VINCENZO ,  GASTALDI ROBERTO ,  MANSTRETTA ALESSANDRO ,  TELECCO NICOLA ,  TORELLI GUIDO

    IPC: G11C11/56

    Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 (n > = 2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a discrete set of m distinct cell current values (IC0-IC15), each cell current value (IC0-IC15) corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current (IC) with a prescribed number of reference currents (IR1,IR2,IR3) having values comprised between a minimum value and a maximum value of said discrete set of m cell current values (IC0-IC15) and dividing said discrete set of m cell current values (IC0-IC15) in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current (IC) belongs; repeating step a) for the sub-set of cell current values to which the cell current (IC) belongs, until the sub-set of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value of the current (IC) of the memory cell (MC) to be sensed.

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